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refactor(io): use MmioBus as the x86 IO bus
There is no need to introduce a new module to model the IO bus. MMIO and IO are basically the same thing except the address width. Signed-off-by: Changyuan Lyu <changyuanl@google.com>
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parent
ee37fa2af9
commit
0580084834
2 changed files with 7 additions and 67 deletions
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@ -13,7 +13,6 @@
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// limitations under the License.
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mod addressable;
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pub mod io;
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pub mod mmio;
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pub mod ram;
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@ -27,12 +26,9 @@ use crate::hv::{self, VmEntry, VmMemory};
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use ram::UserMem;
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use addressable::{Addressable, SlotBackend};
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use io::IoBus;
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use mmio::{Mmio, MmioBus};
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use mmio::{Mmio, MmioBus, MmioRegion};
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use ram::RamBus;
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use self::io::IoDev;
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use crate::arch::layout::{
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MEM_64_START, MMIO_32_START, PCIE_CONFIG_END, PCIE_CONFIG_START, RAM_32_END,
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};
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@ -98,7 +94,7 @@ pub struct Allocator {
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pub struct Memory {
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ram_bus: Arc<RamBus>,
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mmio_bus: MmioBus,
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io_bus: IoBus,
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io_bus: MmioBus,
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// TODO do we need a global lock?
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allocator: Mutex<Allocator>,
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}
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@ -125,7 +121,7 @@ impl Memory {
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ram_bus: Arc::new(RamBus::new(vm_memory)),
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mmio_bus: MmioBus::new(),
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allocator: Mutex::new(Allocator::default()),
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io_bus: IoBus::new(),
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io_bus: MmioBus::new(),
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}
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}
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@ -197,7 +193,7 @@ impl Memory {
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}
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#[cfg(target_arch = "x86_64")]
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pub fn add_io_dev(&self, port: Option<u16>, dev: IoDev) -> Result<u16, Error> {
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pub fn add_io_dev(&self, port: Option<u16>, dev: MmioRegion) -> Result<u16, Error> {
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let mut allocator = self.allocator.lock()?;
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let port = match port {
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Some(port) => {
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@ -221,7 +217,7 @@ impl Memory {
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port as u16
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}
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};
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self.io_bus.add(port, dev)?;
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self.io_bus.add(port as usize, dev)?;
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Ok(port)
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}
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@ -306,13 +302,13 @@ impl Memory {
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}
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}
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if let Some(val) = write {
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match self.io_bus.write(port, size, val) {
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match self.io_bus.write(port as usize, size, val as u64) {
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Ok(()) => Ok(VmEntry::None),
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Err(Error::Action(action)) => self.handle_action(action),
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Err(e) => Err(e),
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}
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} else {
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let data = self.io_bus.read(port, size)?;
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let data = self.io_bus.read(port as usize, size)? as u32;
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Ok(VmEntry::Io { data })
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}
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}
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@ -1,56 +0,0 @@
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// Copyright 2024 Google LLC
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// https://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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use std::sync::{Arc, RwLock};
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use super::mmio::{Mmio, MmioRange};
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use super::Result;
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#[derive(Debug)]
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pub struct IoBus {
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inner: RwLock<MmioRange>,
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}
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pub type IoDev = Arc<dyn Mmio + Send + Sync + 'static>;
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impl Default for IoBus {
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fn default() -> Self {
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Self::new()
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}
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}
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impl IoBus {
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pub fn new() -> IoBus {
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Self {
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inner: RwLock::new(MmioRange::with_size(u16::MAX as usize)),
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}
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}
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pub(super) fn add(&self, port: u16, dev: IoDev) -> Result<()> {
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let mut inner = self.inner.write()?;
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let dev = inner.add(port as usize, dev)?;
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dev.mapped(port as usize)?;
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Ok(())
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}
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pub fn read(&self, port: u16, size: u8) -> Result<u32> {
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let inner = self.inner.read()?;
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inner.read(port as usize, size).map(|v| v as u32)
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}
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pub fn write(&self, port: u16, size: u8, val: u32) -> Result<()> {
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let inner = self.inner.read()?;
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inner.write(port as usize, size, val as u64)
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}
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}
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