From 8baaef0bfcda7b7fc7f75ebc08e2ba0a6a74fad9 Mon Sep 17 00:00:00 2001
From: Changyuan Lyu <changyuanl@google.com>
Date: Sun, 4 Aug 2024 09:58:36 -0700
Subject: [PATCH] fix(cpuid): add cache and TLB information

Signed-off-by: Changyuan Lyu <changyuanl@google.com>
---
 alioth/src/board/x86_64.rs | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/alioth/src/board/x86_64.rs b/alioth/src/board/x86_64.rs
index 2f00062..06ee8f3 100644
--- a/alioth/src/board/x86_64.rs
+++ b/alioth/src/board/x86_64.rs
@@ -80,6 +80,14 @@ impl<V: Vm> ArchBoard<V> {
                 }
             }
         }
+        let highest = unsafe { __cpuid(0x8000_0000) }.eax;
+        for func in [0x8000_0005, 0x8000_0006] {
+            if func > highest {
+                break;
+            }
+            let host_cpuid = unsafe { __cpuid(func) };
+            cpuids.insert(CpuidIn { func, index: None }, host_cpuid);
+        }
         Ok(Self {
             cpuids,
             sev_ap_eip: AtomicU32::new(0),