Vfio: Disable msix bar's mmap

If vfio device's bar is mmappable, vcpu could access it directly through
ept without trapping. But msix's table and pba exist on pci bar, they must
be trapped and emulated by crosvm, so these bars mmappable must be
disabled.

BUG=chromium:992270
TEST=pass through a device with msix cap to guest, then test device
function in guest.

Change-Id: If7504a924902c940e00cc759c1ca64a116bbca17
Signed-off-by: Xiong Zhang <xiong.y.zhang@intel.corp-partner.google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/1987815
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>

devices/src/pci/vfio_pci.rs

@@ -415,6 +415,14 @@ impl VfioMsixCap {
         self.config.write_pba_entries(offset, data);
     }
 
+    fn is_msix_bar(&self, bar_index: u32) -> bool {
+        if bar_index == self.table_pci_bar || bar_index == self.pba_pci_bar {
+            true
+        } else {
+            false
+        }
+    }
+
     fn get_msix_irqfds(&self) -> Option<Vec<&EventFd>> {
         let mut irqfds = Vec::new();
 
@@ -683,6 +691,14 @@ impl VfioPciDevice {
     fn add_bar_mmap(&self, index: u32, bar_addr: u64) -> Vec<MemoryMapping> {
         let mut mem_map: Vec<MemoryMapping> = Vec::new();
         if self.device.get_region_flags(index) & VFIO_REGION_INFO_FLAG_MMAP != 0 {
+            // the bar storing msix table and pba couldn't mmap.
+            // these bars should be trapped, so that msix could be emulated.
+            if let Some(msix_cap) = &self.msix_cap {
+                if msix_cap.is_msix_bar(index) {
+                    return mem_map;
+                }
+            }
+
             let mmaps = self.device.get_region_mmap(index);
             if mmaps.is_empty() {
                 return mem_map;