From 2de0088c9eda27fd68a17736228199b4d97de409 Mon Sep 17 00:00:00 2001 From: Jingkui Wang Date: Sat, 2 Mar 2019 02:37:54 -0800 Subject: [PATCH] make aarch64 pci dma-coherent On arm, if the device is not coherent, guest kernel will allocate dma memory as no-cacheable. Crosvm on the host user space thinks the memory is cacheable. Thus when guest kernel write to dma memory, it will bypass the cache, crosvm won't see the change. BUG=None TEST=local build and test Change-Id: If6cf2d28afec61d5beb136628116ff9e7e0483f4 Reviewed-on: https://chromium-review.googlesource.com/1497739 Commit-Ready: Jingkui Wang Tested-by: Jingkui Wang Reviewed-by: Sonny Rao Reviewed-by: Daniel Verkamp --- aarch64/src/fdt.rs | 1 + 1 file changed, 1 insertion(+) diff --git a/aarch64/src/fdt.rs b/aarch64/src/fdt.rs index e8ab335cb6..ff3274fc11 100644 --- a/aarch64/src/fdt.rs +++ b/aarch64/src/fdt.rs @@ -252,6 +252,7 @@ fn create_pci_nodes( property_u32(fdt, "#interrupt-cells", 1)?; property(fdt, "interrupt-map", &interrupt_map)?; property(fdt, "interrupt-map-mask", &interrupt_map_mask)?; + property_null(fdt, "dma-coherent")?; end_node(fdt)?; Ok(())