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x86_64: set fast REP MOVS bit in IA32_MISC_ENABLE for BIOS too

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This MSR seems to be the responsibility of the hypervisor to set up even
when booting with BIOS/firmware in the guest. When it is missing, the
configuration of IA32_MISC_ENABLE will be inconsistent with CPUID bits
like ERMS and FSRM, which report fast REP MOVSB behavior as well.

Specificially, this avoids a problem with newer Linux kernels when
booted in crosvm with a BIOS where the ERMS feature is masked out due to
the IA32_MISC_ENABLE bit being unset but the FSRM feature is not masked
out, leading to a normally impossible combination of CPUID features that
the memmove code did not expect.

BUG=b:228795137
TEST=Boot Linux with OVMF on brya

Change-Id: I9e9e8301d8cb3d1f0f0d0c7d2137ff3286f35c1d
Reviewed-on: https://chromium-review.googlesource.com/c/crosvm/crosvm/+/3919374
Reviewed-by: Dennis Kempin <denniskempin@google.com>
Commit-Queue: Daniel Verkamp <dverkamp@chromium.org>
Reviewed-by: Mike Gerow <gerow@google.com>
This commit is contained in:
Daniel Verkamp 2022-09-26 15:27:25 -07:00 committed by crosvm LUCI
parent 6af40edd41
commit 31a517d5e2
1 changed files with 10 additions and 4 deletions
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14
x86_64/src/regs.rs
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@ -160,10 +160,16 @@ pub fn mtrr_msrs(vm: &dyn Vm, pci_start: u64) -> Vec<Register> {
///
/// Currently only sets IA32_TSC to 0.
pub fn default_msrs() -> Vec<Register> {
vec![Register {
id: crate::msr_index::MSR_IA32_TSC,
value: 0x0,
}]
vec![
Register {
id: crate::msr_index::MSR_IA32_TSC,
value: 0x0,
},
Register {
id: crate::msr_index::MSR_IA32_MISC_ENABLE,
value: crate::msr_index::MSR_IA32_MISC_ENABLE_FAST_STRING as u64,
},
]
}
/// Configure Model specific registers for long (64-bit) mode.