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pci-bridge: Set limit smaller than base at initialize

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According to pci bridge spec, the io/mem/prefetch mem limit register
must be programmed to a smaller value than the corresponding base register
if there is no io/mem/prefetch mem on the secondary side of the brige.

When bridge is created, it doesn't have any child device, then
no io/mem/prefetch mem on the secondary side of the bridge, so this
patch set limit to 0, but base to 0xffff.

When a device is attached behind the bridge, kernel will assign
resource and set the right value to these base and limit register.

BUG=b:199442120
BUG=b:185084350
TEST=crosvm run --bios OVMF.fd
TEST=hotplug in/out a pcie device to pcie root port repeatly

Change-Id: Id1c2ff1132d59e1aafd548fc17ab5aee2023dd8c
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3166883
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
Commit-Queue: Daniel Verkamp <dverkamp@chromium.org>
This commit is contained in:
Xiong Zhang 2021-09-17 10:47:36 +08:00 committed by Commit Bot
parent 9557588786
commit 6d1b2df054
1 changed files with 3 additions and 0 deletions
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3
devices/src/pci/pci_configuration.rs
View file

@ -317,8 +317,11 @@ impl PciConfiguration {
registers[3] = 0x0001_0000; // Header type 1 (bridge)
writable_bits[6] = 0x00ff_ffff; // Primary/secondary/subordinate bus number,
// secondary latency timer
registers[7] = 0x0000_00f0; // IO base > IO Limit, no IO address on secondary side at initialize
writable_bits[7] = 0xf900_0000; // IO base and limit, secondary status,
registers[8] = 0x0000_fff0; // mem base > mem Limit, no MMIO address on secondary side at initialize
writable_bits[8] = 0xfff0_fff0; // Memory base and limit
registers[9] = 0x0001_fff1; // pmem base > pmem Limit, no prefetch MMIO address on secondary side at initialize
writable_bits[9] = 0xfff0_fff0; // Prefetchable base and limit
writable_bits[10] = 0xffff_ffff; // Prefetchable base upper 32 bits
writable_bits[11] = 0xffff_ffff; // Prefetchable limit upper 32 bits