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https://chromium.googlesource.com/crosvm/crosvm
synced 2025-02-05 18:20:34 +00:00
acpi: refactor PM1 virtualization
- Refactor read() and write() for ACPIPMResource to protect against PIO accesses across PM1 register boundaries, and properly support byte accesses. - If compiled with the feature "direct", all writes to SLP_TYP are interpreted as S5 since _Sx is platform-specific. - Remove Sleep Control and Status Registers since they are only used on HW-Reduced ACPI systems. BUG=b:199383670 TEST=boot Linux kernel and shut down Change-Id: Iaf9fdf5a161eb6f5618235c3a66f8817258ce289 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3350489 Reviewed-by: Daniel Verkamp <dverkamp@chromium.org> Tested-by: kokoro <noreply+kokoro@google.com> Commit-Queue: Tomasz Nowicki <tnowicki@google.com>
This commit is contained in:
Peter Fang
Commit Bot
parent
90922be6d6
commit
80e6d5bf65
1 changed files with 128 additions and 69 deletions
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@ -7,18 +7,18 @@ use acpi_tables::{aml, aml::Aml};
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use base::{error, warn, Event};
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/// ACPI PM resource for handling OS suspend/resume request
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#[allow(dead_code)]
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pub struct ACPIPMResource {
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suspend_evt: Event,
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exit_evt: Event,
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pm1_status: u16,
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pm1_enable: u16,
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pm1_control: u16,
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sleep_control: u8,
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sleep_status: u8,
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}
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impl ACPIPMResource {
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/// Constructs ACPI Power Management Resouce.
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#[allow(dead_code)]
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pub fn new(suspend_evt: Event, exit_evt: Event) -> ACPIPMResource {
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ACPIPMResource {
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suspend_evt,
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@ -26,8 +26,6 @@ impl ACPIPMResource {
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pm1_status: 0,
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pm1_enable: 0,
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pm1_control: 0,
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sleep_control: 0,
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sleep_status: 0,
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}
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}
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}
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@ -38,18 +36,36 @@ pub const ACPIPM_RESOURCE_EVENTBLK_LEN: u8 = 4;
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pub const ACPIPM_RESOURCE_CONTROLBLK_LEN: u8 = 2;
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/// ACPI PM register value definitions
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const PM1_STATUS: u16 = 0;
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const PM1_ENABLE: u16 = 2;
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const PM1_CONTROL: u16 = 4;
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const SLEEP_CONTROL: u16 = 6;
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const SLEEP_STATUS: u16 = 7;
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const BITMASK_PM1CNT_SLEEP_ENABLE: u16 = 0x2000;
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const BITMASK_SLEEPCNT_SLEEP_ENABLE: u8 = 0x20;
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const BITMASK_PM1CNT_WAKE_STATUS: u16 = 0x8000;
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const BITMASK_SLEEPCNT_WAKE_STATUS: u8 = 0x80;
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/// 4.8.4.1.1 PM1 Status Registers, ACPI Spec Version 6.4
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/// Register Location: <PM1a_EVT_BLK / PM1b_EVT_BLK> System I/O or Memory Space (defined in FADT)
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/// Size: PM1_EVT_LEN / 2 (defined in FADT)
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const PM1_STATUS: u16 = 0;
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/// 4.8.4.1.2 PM1Enable Registers, ACPI Spec Version 6.4
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/// Register Location: <<PM1a_EVT_BLK / PM1b_EVT_BLK> + PM1_EVT_LEN / 2 System I/O or Memory Space
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/// (defined in FADT)
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/// Size: PM1_EVT_LEN / 2 (defined in FADT)
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const PM1_ENABLE: u16 = PM1_STATUS + (ACPIPM_RESOURCE_EVENTBLK_LEN as u16 / 2);
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/// 4.8.4.2.1 PM1 Control Registers, ACPI Spec Version 6.4
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/// Register Location: <PM1a_CNT_BLK / PM1b_CNT_BLK> System I/O or Memory Space (defined in FADT)
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/// Size: PM1_CNT_LEN (defined in FADT)
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const PM1_CONTROL: u16 = PM1_STATUS + ACPIPM_RESOURCE_EVENTBLK_LEN as u16;
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const BITMASK_PM1CNT_SLEEP_ENABLE: u16 = 0x2000;
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const BITMASK_PM1CNT_WAKE_STATUS: u16 = 0x8000;
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#[cfg(not(feature = "direct"))]
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const BITMASK_PM1CNT_SLEEP_TYPE: u16 = 0x1C00;
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const SLEEP_TYPE_S5: u16 = 0;
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#[cfg(not(feature = "direct"))]
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const SLEEP_TYPE_S1: u16 = 1 << 10;
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#[cfg(not(feature = "direct"))]
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const SLEEP_TYPE_S5: u16 = 0 << 10;
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const PM1_STATUS_LAST: u16 = PM1_STATUS + (ACPIPM_RESOURCE_EVENTBLK_LEN as u16 / 2) - 1;
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const PM1_ENABLE_LAST: u16 = PM1_ENABLE + (ACPIPM_RESOURCE_EVENTBLK_LEN as u16 / 2) - 1;
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const PM1_CONTROL_LAST: u16 = PM1_CONTROL + ACPIPM_RESOURCE_CONTROLBLK_LEN as u16 - 1;
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impl BusDevice for ACPIPMResource {
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fn debug_label(&self) -> String {
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@ -57,69 +73,116 @@ impl BusDevice for ACPIPMResource {
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}
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fn read(&mut self, info: BusAccessInfo, data: &mut [u8]) {
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let val = match info.offset as u16 {
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PM1_STATUS => self.pm1_status,
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PM1_ENABLE => self.pm1_enable,
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PM1_CONTROL => self.pm1_control,
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SLEEP_CONTROL => self.sleep_control as u16,
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SLEEP_STATUS => self.sleep_status as u16,
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match info.offset as u16 {
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// Accesses to the PM1 registers are done through byte or word accesses
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PM1_STATUS..=PM1_STATUS_LAST => {
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if data.len() > std::mem::size_of::<u16>()
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|| info.offset + data.len() as u64 > (PM1_STATUS_LAST + 1).into()
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{
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warn!("ACPIPM: bad read size: {}", data.len());
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return;
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}
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let offset = (info.offset - PM1_STATUS as u64) as usize;
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data.copy_from_slice(&self.pm1_status.to_ne_bytes()[offset..offset + data.len()]);
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}
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PM1_ENABLE..=PM1_ENABLE_LAST => {
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if data.len() > std::mem::size_of::<u16>()
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|| info.offset + data.len() as u64 > (PM1_ENABLE_LAST + 1).into()
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{
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warn!("ACPIPM: bad read size: {}", data.len());
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return;
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}
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let offset = (info.offset - PM1_ENABLE as u64) as usize;
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data.copy_from_slice(&self.pm1_enable.to_ne_bytes()[offset..offset + data.len()]);
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}
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PM1_CONTROL..=PM1_CONTROL_LAST => {
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if data.len() > std::mem::size_of::<u16>()
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|| info.offset + data.len() as u64 > (PM1_CONTROL_LAST + 1).into()
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{
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warn!("ACPIPM: bad read size: {}", data.len());
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return;
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}
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let offset = (info.offset - PM1_CONTROL as u64) as usize;
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data.copy_from_slice(&self.pm1_control.to_ne_bytes()[offset..offset + data.len()]);
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}
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_ => {
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warn!("ACPIPM: Bad read from {}", info);
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return;
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}
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};
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let val_arr = val.to_ne_bytes();
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for i in 0..std::mem::size_of::<u16>() {
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if i < data.len() {
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data[i] = val_arr[i];
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}
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}
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}
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fn write(&mut self, info: BusAccessInfo, data: &[u8]) {
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let max_bytes = std::mem::size_of::<u16>();
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// only allow maximum max_bytes to write
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if data.len() > max_bytes {
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warn!("ACPIPM: bad write size: {}", data.len());
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return;
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}
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let mut val_arr = u16::to_ne_bytes(0u16);
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for i in 0..std::mem::size_of::<u16>() {
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if i < data.len() {
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val_arr[i] = data[i];
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}
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}
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let val = u16::from_ne_bytes(val_arr);
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match info.offset as u16 {
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PM1_STATUS => self.pm1_status &= !val,
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PM1_ENABLE => self.pm1_enable = val,
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PM1_CONTROL => {
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if (val & BITMASK_PM1CNT_SLEEP_ENABLE) == BITMASK_PM1CNT_SLEEP_ENABLE {
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if val & BITMASK_PM1CNT_SLEEP_TYPE == SLEEP_TYPE_S5 {
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if let Err(e) = self.exit_evt.write(1) {
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error!("ACPIPM: failed to trigger exit event: {}", e);
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// Accesses to the PM1 registers are done through byte or word accesses
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PM1_STATUS..=PM1_STATUS_LAST => {
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if data.len() > std::mem::size_of::<u16>()
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|| info.offset + data.len() as u64 > (PM1_STATUS_LAST + 1).into()
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{
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warn!("ACPIPM: bad write size: {}", data.len());
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return;
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}
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let offset = (info.offset - PM1_STATUS as u64) as usize;
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let mut v = self.pm1_status.to_ne_bytes();
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for (i, j) in (offset..offset + data.len()).enumerate() {
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v[j] &= !data[i];
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}
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self.pm1_status = u16::from_ne_bytes(v);
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}
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PM1_ENABLE..=PM1_ENABLE_LAST => {
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if data.len() > std::mem::size_of::<u16>()
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|| info.offset + data.len() as u64 > (PM1_ENABLE_LAST + 1).into()
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{
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warn!("ACPIPM: bad write size: {}", data.len());
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return;
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}
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let offset = (info.offset - PM1_ENABLE as u64) as usize;
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let mut v = self.pm1_enable.to_ne_bytes();
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for (i, j) in (offset..offset + data.len()).enumerate() {
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v[j] = data[i];
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}
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self.pm1_enable = u16::from_ne_bytes(v);
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}
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PM1_CONTROL..=PM1_CONTROL_LAST => {
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if data.len() > std::mem::size_of::<u16>()
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|| info.offset + data.len() as u64 > (PM1_CONTROL_LAST + 1).into()
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{
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warn!("ACPIPM: bad write size: {}", data.len());
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return;
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}
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let offset = (info.offset - PM1_CONTROL as u64) as usize;
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let mut v = self.pm1_control.to_ne_bytes();
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for (i, j) in (offset..offset + data.len()).enumerate() {
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v[j] = data[i];
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}
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let val = u16::from_ne_bytes(v);
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// SLP_EN is a write-only bit and reads to it always return a zero
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if (val & BITMASK_PM1CNT_SLEEP_ENABLE) != 0 {
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// only support S5 in direct mode
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#[cfg(feature = "direct")]
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if let Err(e) = self.exit_evt.write(1) {
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error!("ACPIPM: failed to trigger exit event: {}", e);
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}
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#[cfg(not(feature = "direct"))]
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match val & BITMASK_PM1CNT_SLEEP_TYPE {
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SLEEP_TYPE_S1 => {
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if let Err(e) = self.suspend_evt.write(1) {
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error!("ACPIPM: failed to trigger suspend event: {}", e);
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}
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}
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} else if let Err(e) = self.suspend_evt.write(1) {
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error!("ACPIPM: failed to trigger suspend event: {}", e);
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SLEEP_TYPE_S5 => {
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if let Err(e) = self.exit_evt.write(1) {
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error!("ACPIPM: failed to trigger exit event: {}", e);
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}
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}
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_ => error!(
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"ACPIPM: unknown SLP_TYP written: {}",
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(val & BITMASK_PM1CNT_SLEEP_TYPE) >> 10
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),
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}
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}
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self.pm1_control = val & !BITMASK_PM1CNT_SLEEP_ENABLE;
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}
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SLEEP_CONTROL => {
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let sleep_control = val as u8;
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if (sleep_control & BITMASK_SLEEPCNT_SLEEP_ENABLE) == BITMASK_SLEEPCNT_SLEEP_ENABLE
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{
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if let Err(e) = self.suspend_evt.write(1) {
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error!("ACPIPM: failed to trigger suspend event: {}", e);
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}
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}
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self.sleep_control = sleep_control as u8 & !BITMASK_SLEEPCNT_SLEEP_ENABLE;
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}
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SLEEP_STATUS => self.sleep_status &= !val as u8,
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_ => {
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warn!("ACPIPM: Bad write to {}", info);
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}
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@ -129,11 +192,7 @@ impl BusDevice for ACPIPMResource {
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impl BusResumeDevice for ACPIPMResource {
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fn resume_imminent(&mut self) {
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let val = self.pm1_status;
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self.pm1_status = val | BITMASK_PM1CNT_WAKE_STATUS;
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let val = self.sleep_status;
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self.sleep_status = val | BITMASK_SLEEPCNT_WAKE_STATUS;
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self.pm1_status |= BITMASK_PM1CNT_WAKE_STATUS;
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}
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}
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