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https://chromium.googlesource.com/crosvm/crosvm
synced 2025-02-05 10:10:41 +00:00
crosvm: Minimal change for manatee memory mapping.
Do not map RAM to where the coreboot regions are. Shift boot time GDT and IDT a bit to make way for coreboot region at 0..fff. BUG=b:188011323 TEST=boot volteer-manatee TEST=tast run rammus-arc-r arc.Boot.vm # ARCVM still boots. TEST=tast run rammus-arc-r crostini.Basic.bullseye_stable volteer-manatee memory map: after: localhost ~ # dmesg | grep e820 [ 0.000000] BIOS-e820: [mem 0x0000000000000000-0x000000000009fbff] usable [ 0.000000] BIOS-e820: [mem 0x0000000000200000-0x00000000cfffffff] usable [ 0.000000] BIOS-e820: [mem 0x00000000f4000000-0x00000000f7ffffff] reserved [ 0.000000] BIOS-e820: [mem 0x0000000100000000-0x00000003f05fffff] usable before: localhost ~ # dmesg | grep e820 [ 0.000000] BIOS-e820: [mem 0x0000000000001000-0x000000000009fbff] usable [ 0.000000] BIOS-e820: [mem 0x0000000000200000-0x000000005fffffff] usable [ 0.000000] BIOS-e820: [mem 0x00000000f4000000-0x00000000f7ffffff] reserved [ 0.000000] BIOS-e820: [mem 0x0000000100000000-0x0000000460600fff] usable Change-Id: Ifa19988c444d79dc81eb77c59e5b5434abf883fb Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3405402 Reviewed-by: Daniel Verkamp <dverkamp@chromium.org> Tested-by: kokoro <noreply+kokoro@google.com> Commit-Queue: Junichi Uekawa <uekawa@chromium.org>
This commit is contained in:
Junichi Uekawa
Commit Bot
parent
57d7eba097
commit
8764deb8dd
4 changed files with 83 additions and 28 deletions
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@ -104,7 +104,7 @@ chromeos = ["base/chromeos", "audio_cras", "devices/chromeos"]
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composite-disk = ["protos/composite-disk", "protobuf", "disk/composite-disk"]
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default = ["audio", "gpu", "usb"]
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default-no-sandbox = []
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direct = ["devices/direct"]
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direct = ["devices/direct", "x86_64/direct"]
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gdb = ["gdbstub", "gdbstub_arch", "arch/gdb", "vm_control/gdb", "x86_64/gdb"]
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gfxstream = ["devices/gfxstream"]
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gpu = ["devices/gpu"]
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@ -6,6 +6,7 @@ edition = "2018"
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[features]
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gdb = ["gdbstub_arch", "arch/gdb"]
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direct = []
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[dependencies]
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arch = { path = "../arch" }
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@ -195,7 +195,18 @@ const GB: u64 = 1 << 30;
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const BOOT_STACK_POINTER: u64 = 0x8000;
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// Make sure it align to 256MB for MTRR convenient
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const MEM_32BIT_GAP_SIZE: u64 = 768 * MB;
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const MEM_32BIT_GAP_SIZE: u64 = if cfg!(feature = "direct") {
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// Allow space for identity mapping coreboot memory regions on the host
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// which is found at around 7a00_0000 (little bit before 2GB)
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//
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// TODO(b/188011323): stop hardcoding sizes and addresses here and instead
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// determine the memory map from how the VM has been configured via the
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// command line.
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2560 * MB
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} else {
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768 * MB
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};
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const START_OF_RAM_32BITS: u64 = if cfg!(feature = "direct") { 0x1000 } else { 0 };
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const FIRST_ADDR_PAST_32BITS: u64 = 1 << 32;
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// Reserved memory for nand_bios/LAPIC/IOAPIC/HPET/.....
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const RESERVED_MEM_SIZE: u64 = 0x800_0000;
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@ -264,7 +275,12 @@ fn configure_system(
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params.hdr.ramdisk_size = initrd_size as u32;
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}
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add_e820_entry(&mut params, 0, EBDA_START, E820Type::Ram)?;
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add_e820_entry(
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&mut params,
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START_OF_RAM_32BITS,
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EBDA_START - START_OF_RAM_32BITS,
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E820Type::Ram,
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)?;
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let mem_end = guest_mem.end_addr();
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if mem_end < end_32bit_gap_start {
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@ -334,18 +350,21 @@ fn add_e820_entry(
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/// For x86_64 all addresses are valid from the start of the kernel except a
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/// carve out at the end of 32bit address space.
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fn arch_memory_regions(size: u64, bios_size: Option<u64>) -> Vec<(GuestAddress, u64)> {
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let mem_end = GuestAddress(size);
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let mem_start = START_OF_RAM_32BITS;
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let mem_end = GuestAddress(size + mem_start);
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let first_addr_past_32bits = GuestAddress(FIRST_ADDR_PAST_32BITS);
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let end_32bit_gap_start = GuestAddress(END_ADDR_BEFORE_32BITS);
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let mut regions = Vec::new();
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if mem_end <= end_32bit_gap_start {
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regions.push((GuestAddress(0), size));
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regions.push((GuestAddress(mem_start), size));
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if let Some(bios_size) = bios_size {
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regions.push((bios_start(bios_size), bios_size));
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}
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} else {
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regions.push((GuestAddress(0), end_32bit_gap_start.offset()));
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regions.push((
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GuestAddress(mem_start),
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end_32bit_gap_start.offset() - mem_start,
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));
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if let Some(bios_size) = bios_size {
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regions.push((bios_start(bios_size), bios_size));
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}
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@ -1364,27 +1383,29 @@ mod tests {
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#[test]
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fn regions_lt_4gb_nobios() {
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let regions = arch_memory_regions(1u64 << 29, /* bios_size */ None);
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let regions = arch_memory_regions(512 * MB, /* bios_size */ None);
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assert_eq!(1, regions.len());
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assert_eq!(GuestAddress(0), regions[0].0);
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assert_eq!(GuestAddress(START_OF_RAM_32BITS), regions[0].0);
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assert_eq!(1u64 << 29, regions[0].1);
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}
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#[test]
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fn regions_gt_4gb_nobios() {
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let regions = arch_memory_regions((1u64 << 32) + 0x8000, /* bios_size */ None);
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let size = 4 * GB + 0x8000;
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let regions = arch_memory_regions(size, /* bios_size */ None);
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assert_eq!(2, regions.len());
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assert_eq!(GuestAddress(0), regions[0].0);
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assert_eq!(GuestAddress(1u64 << 32), regions[1].0);
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assert_eq!(GuestAddress(START_OF_RAM_32BITS), regions[0].0);
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assert_eq!(GuestAddress(4 * GB), regions[1].0);
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assert_eq!(4 * GB + 0x8000, regions[0].1 + regions[1].1);
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}
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#[test]
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fn regions_lt_4gb_bios() {
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let bios_len = 1 * MB;
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let regions = arch_memory_regions(1u64 << 29, Some(bios_len));
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let regions = arch_memory_regions(512 * MB, Some(bios_len));
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assert_eq!(2, regions.len());
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assert_eq!(GuestAddress(0), regions[0].0);
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assert_eq!(1u64 << 29, regions[0].1);
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assert_eq!(GuestAddress(START_OF_RAM_32BITS), regions[0].0);
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assert_eq!(512 * MB, regions[0].1);
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assert_eq!(
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GuestAddress(FIRST_ADDR_PAST_32BITS - bios_len),
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regions[1].0
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@ -1395,38 +1416,71 @@ mod tests {
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#[test]
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fn regions_gt_4gb_bios() {
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let bios_len = 1 * MB;
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let regions = arch_memory_regions((1u64 << 32) + 0x8000, Some(bios_len));
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let regions = arch_memory_regions(4 * GB + 0x8000, Some(bios_len));
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assert_eq!(3, regions.len());
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assert_eq!(GuestAddress(0), regions[0].0);
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assert_eq!(GuestAddress(START_OF_RAM_32BITS), regions[0].0);
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assert_eq!(
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GuestAddress(FIRST_ADDR_PAST_32BITS - bios_len),
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regions[1].0
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);
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assert_eq!(bios_len, regions[1].1);
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assert_eq!(GuestAddress(1u64 << 32), regions[2].0);
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assert_eq!(GuestAddress(4 * GB), regions[2].0);
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}
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#[test]
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fn regions_eq_4gb_nobios() {
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// Test with size = 3328, which is exactly 4 GiB minus the size of the gap (768 MB).
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let regions = arch_memory_regions(3328 * MB, /* bios_size */ None);
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// Test with exact size of 4GB - the overhead.
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let regions = arch_memory_regions(
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4 * GB - MEM_32BIT_GAP_SIZE - START_OF_RAM_32BITS,
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/* bios_size */ None,
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);
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dbg!(®ions);
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assert_eq!(1, regions.len());
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assert_eq!(GuestAddress(0), regions[0].0);
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assert_eq!(3328 * MB, regions[0].1);
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assert_eq!(GuestAddress(START_OF_RAM_32BITS), regions[0].0);
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assert_eq!(
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4 * GB - MEM_32BIT_GAP_SIZE - START_OF_RAM_32BITS,
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regions[0].1
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);
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}
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#[test]
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fn regions_eq_4gb_bios() {
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// Test with size = 3328, which is exactly 4 GiB minus the size of the gap (768 MB).
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// Test with exact size of 4GB - the overhead.
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let bios_len = 1 * MB;
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let regions = arch_memory_regions(3328 * MB, Some(bios_len));
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let regions = arch_memory_regions(
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4 * GB - MEM_32BIT_GAP_SIZE - START_OF_RAM_32BITS,
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Some(bios_len),
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);
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assert_eq!(2, regions.len());
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assert_eq!(GuestAddress(0), regions[0].0);
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assert_eq!(3328 * MB, regions[0].1);
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assert_eq!(GuestAddress(START_OF_RAM_32BITS), regions[0].0);
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assert_eq!(
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4 * GB - MEM_32BIT_GAP_SIZE - START_OF_RAM_32BITS,
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regions[0].1
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);
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assert_eq!(
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GuestAddress(FIRST_ADDR_PAST_32BITS - bios_len),
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regions[1].0
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);
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assert_eq!(bios_len, regions[1].1);
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}
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#[test]
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#[cfg(feature = "direct")]
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fn end_addr_before_32bits() {
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// On volteer, type16 (coreboot) region is at 0x00000000769f3000-0x0000000076ffffff.
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// On brya, type16 region is at 0x0000000076876000-0x00000000803fffff
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let brya_type16_address = 0x7687_6000;
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assert!(
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END_ADDR_BEFORE_32BITS < brya_type16_address,
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"{} < {}",
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END_ADDR_BEFORE_32BITS,
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brya_type16_address
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);
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}
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#[test]
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fn check_32bit_gap_size_alignment() {
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// 32bit gap memory is 256 MB aligned to be friendly for MTRR mappings.
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assert_eq!(MEM_32BIT_GAP_SIZE % (256 * MB), 0);
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}
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}
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@ -244,8 +244,8 @@ const X86_CR4_PAE: u64 = 0x20;
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const EFER_LME: u64 = 0x100;
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const EFER_LMA: u64 = 0x400;
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const BOOT_GDT_OFFSET: u64 = 0x500;
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const BOOT_IDT_OFFSET: u64 = 0x520;
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const BOOT_GDT_OFFSET: u64 = 0x1500;
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const BOOT_IDT_OFFSET: u64 = 0x1520;
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const BOOT_GDT_MAX: usize = 4;
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