From 9ba5f665fc20c1cd98e778486b6265a055aeb457 Mon Sep 17 00:00:00 2001 From: Keiichi Watanabe Date: Tue, 8 Feb 2022 01:15:02 +0900 Subject: [PATCH] devices: pci: Use bit_field for MSI-X message control register This will allow reusing `MsixCap` for virtio-vhost-user in the later CLs. BUG=b:194136484 TEST=cargo test Change-Id: I38bced958d42ce7e3192a54564628c9b559c4269 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3446521 Tested-by: kokoro Reviewed-by: Alexandre Courbot Commit-Queue: Keiichi Watanabe --- devices/src/pci/msix.rs | 32 +++++++++++++++++++++++--------- 1 file changed, 23 insertions(+), 9 deletions(-) diff --git a/devices/src/pci/msix.rs b/devices/src/pci/msix.rs index 1c8a3e02e7..9268ada942 100644 --- a/devices/src/pci/msix.rs +++ b/devices/src/pci/msix.rs @@ -2,15 +2,15 @@ // Use of this source code is governed by a BSD-style license that can be // found in the LICENSE file. -use crate::pci::{PciCapability, PciCapabilityID}; use base::{error, AsRawDescriptor, Error as SysError, Event, RawDescriptor, Tube, TubeError}; - +use bit_field::*; +use data_model::DataInit; use remain::sorted; use std::convert::TryInto; use thiserror::Error; use vm_control::{VmIrqRequest, VmIrqResponse}; -use data_model::DataInit; +use crate::pci::{PciCapability, PciCapabilityID}; const MAX_MSIX_VECTORS_PER_DEVICE: u16 = 2048; pub const MSIX_TABLE_ENTRIES_MODULO: u64 = 16; @@ -516,6 +516,21 @@ impl AsRawDescriptor for MsixConfig { } } +/// Message Control Register +// 10-0: MSI-X Table size +// 13-11: Reserved +// 14: Mask. Mask all MSI-X when set. +// 15: Enable. Enable all MSI-X when set. +// See for the details. +#[bitfield] +#[derive(Copy, Clone, Default)] +pub struct MsixCtrl { + table_size: B10, + reserved: B4, + mask: B1, + enable: B1, +} + // It is safe to implement DataInit; all members are simple numbers and any value is valid. unsafe impl DataInit for MsixCap {} @@ -528,11 +543,7 @@ pub struct MsixCap { _cap_vndr: u8, _cap_next: u8, // Message Control Register - // 10-0: MSI-X Table size - // 13-11: Reserved - // 14: Mask. Mask all MSI-X when set. - // 15: Enable. Enable all MSI-X when set. - msg_ctl: u16, + msg_ctl: MsixCtrl, // Table. Contains the offset and the BAR indicator (BIR) // 2-0: Table BAR indicator (BIR). Can be 0 to 5. // 31-3: Table offset in the BAR pointed by the BIR. @@ -569,7 +580,10 @@ impl MsixCap { assert!(table_size < MAX_MSIX_VECTORS_PER_DEVICE); // Set the table size and enable MSI-X. - let msg_ctl: u16 = MSIX_ENABLE_BIT + table_size - 1; + let mut msg_ctl = MsixCtrl::new(); + msg_ctl.set_enable(1); + // Table Size is N - 1 encoded. + msg_ctl.set_table_size(table_size - 1); MsixCap { _cap_vndr: 0,