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pci: Add serial bus subclass

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Add serial bus subclass

BUG=chromium:831850
TEST=cargo test

Change-Id: Iffd7a27b5cb423c928f0108b16fb58558cf7bcd4
Reviewed-on: https://chromium-review.googlesource.com/1152212
Commit-Ready: Jingkui Wang <jkwang@google.com>
Tested-by: Jingkui Wang <jkwang@google.com>
Reviewed-by: Dylan Reid <dgreid@chromium.org>
This commit is contained in:
Jingkui Wang 2018-07-26 14:32:42 -07:00 committed by chrome-bot
parent 448516e3f9
commit c1ce54a9dd
1 changed files with 16 additions and 0 deletions
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16
devices/src/pci/pci_configuration.rs
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@ -100,6 +100,22 @@ impl PciSubclass for PciBridgeSubclass {
}
}
/// Subclass of the SerialBus
#[allow(dead_code)]
#[derive(Copy, Clone)]
pub enum PciSerialBusSubClass {
Firewire = 0x00,
ACCESSbus = 0x01,
SSA = 0x02,
USB = 0x03,
}
impl PciSubclass for PciSerialBusSubClass {
fn get_register_value(&self) -> u8 {
*self as u8
}
}
/// Contains the configuration space of a PCI node.
/// See the [specification](https://en.wikipedia.org/wiki/PCI_configuration_space).
/// The configuration space is accessed with DWORD reads and writes from the guest.