From c80de3af0e80e5e8ca532e1ab19240db8466d9c5 Mon Sep 17 00:00:00 2001 From: Masami Hiramatsu Date: Fri, 21 Oct 2022 18:43:01 +0900 Subject: [PATCH] aarch64: Fix Goldfish battery to send IRQ correctly Since the virtio allocates all available IRQ lines for VGIC, system_allocator::allocate_irq() returns 32 for Goldfish battery, but that is not handled by the VGIC. In the result, the interrupts from Goldfish Battery device are dropped in the host kernel. Thus even if the crosvm detects the AC unplug, it is not notified to the guest. To fix this issue, assign a static IRQ number (#3) to Goldfish battery device as same as other devices, so that it can deriver the interrupts correctly to the guest side via VGIC. BUG=b:252582345 TEST=Boot the ARCVM and run 'dumpsys battery' and unplug/re-plug AC connector several times, and confirm the AC status is updated. Change-Id: Icdf3713cdf615d0039dd4e7719b80cad32333094 Reviewed-on: https://chromium-review.googlesource.com/c/crosvm/crosvm/+/3971137 Reviewed-by: Masami Hiramatsu Reviewed-by: Keiichi Watanabe Commit-Queue: Keiichi Watanabe Auto-Submit: Masami Hiramatsu --- aarch64/src/lib.rs | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/aarch64/src/lib.rs b/aarch64/src/lib.rs index fc92573d28..ada0554691 100644 --- a/aarch64/src/lib.rs +++ b/aarch64/src/lib.rs @@ -131,6 +131,9 @@ const AARCH64_RTC_SIZE: u64 = 0x1000; // The RTC device gets the second interrupt line const AARCH64_RTC_IRQ: u32 = 1; +// The Goldfish battery device gets the 3rd interrupt line +const AARCH64_BAT_IRQ: u32 = 3; + // Place the virtual watchdog device at page 3 const AARCH64_VMWDT_ADDR: u64 = 0x3000; // The virtual watchdog device gets one 4k page @@ -144,8 +147,8 @@ const AARCH64_PCI_CFG_SIZE: u64 = 0x1000000; const AARCH64_MMIO_BASE: u64 = 0x2000000; // Size of the whole MMIO region. const AARCH64_MMIO_SIZE: u64 = 0x2000000; -// Virtio devices start at SPI interrupt number 3 -const AARCH64_IRQ_BASE: u32 = 3; +// Virtio devices start at SPI interrupt number 4 +const AARCH64_IRQ_BASE: u32 = 4; // PMU PPI interrupt, same as qemu const AARCH64_PMU_IRQ: u32 = 7; @@ -542,7 +545,7 @@ impl arch::LinuxArch for AArch64 { let (bat_control, bat_mmio_base_and_irq) = match bat_type { Some(BatteryType::Goldfish) => { - let bat_irq = system_allocator.allocate_irq().ok_or(Error::AllocateIrq)?; + let bat_irq = AARCH64_BAT_IRQ; // a dummy AML buffer. Aarch64 crosvm doesn't use ACPI. let mut amls = Vec::new();