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https://chromium.googlesource.com/crosvm/crosvm
synced 2025-02-06 02:25:23 +00:00
devices: pcie: add pcie port structure
Since all pcie ports (root port, upstream port, downstream port) have similiar pci config space and handling logic, we could have a common code base for them to use for code simplicity. This patch adds the code base PciePort structure that could be used later for both pcie root port and pcie upstream/downstream port. BUG=b:199986018 TEST=./tools/presubmit Change-Id: I23cfaf561432ed2cb977d0d2a020fc05370bb4b0 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3692429 Reviewed-by: Daniel Verkamp <dverkamp@chromium.org> Tested-by: kokoro <noreply+kokoro@google.com> Commit-Queue: Daniel Verkamp <dverkamp@chromium.org>
This commit is contained in:
Tinghao Zhang
Chromeos LUCI
parent
9b7e350656
commit
c96e46c6a9
1 changed files with 445 additions and 0 deletions
445
devices/src/pci/pcie/pcie_port.rs
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445
devices/src/pci/pcie/pcie_port.rs
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// Copyright 2022 The ChromiumOS Authors.
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// Use of this source code is governed by a BSD-style license that can be
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// found in the LICENSE file.
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use std::str::FromStr;
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use std::sync::Arc;
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use crate::pci::pci_configuration::PciCapabilityID;
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use crate::pci::{MsiConfig, PciAddress, PciDeviceError};
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use crate::pci::pcie::pci_bridge::PciBridgeBusRange;
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use crate::pci::pcie::pcie_device::PmcConfig;
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use crate::pci::pcie::pcie_host::PcieHostPort;
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use crate::pci::pcie::*;
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use base::warn;
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use data_model::DataInit;
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use resources::{Alloc, SystemAllocator};
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use sync::Mutex;
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// reserve 8MB memory window
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const PCIE_BR_MEM_SIZE: u64 = 0x80_0000;
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// reserve 64MB prefetch window
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const PCIE_BR_PREF_MEM_SIZE: u64 = 0x400_0000;
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pub struct PciePort {
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device_id: u16,
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debug_label: String,
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pci_address: Option<PciAddress>,
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bus_range: PciBridgeBusRange,
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pcie_host: Option<PcieHostPort>,
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pcie_cap_reg_idx: Option<usize>,
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pmc_cap_reg_idx: Option<usize>,
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msi_config: Option<Arc<Mutex<MsiConfig>>>,
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pmc_config: PmcConfig,
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slot_control: Option<u16>,
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slot_status: u16,
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root_control: u16,
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root_status: u32,
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hp_interrupt_pending: bool,
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pme_pending_request_id: Option<PciAddress>,
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prepare_hotplug: bool,
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removed_downstream_valid: bool,
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}
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impl PciePort {
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/// Constructs a new PCIE port
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pub fn new(
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device_id: u16,
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debug_label: String,
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primary_bus_num: u8,
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secondary_bus_num: u8,
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slot_implemented: bool,
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) -> Self {
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let bus_range = PciBridgeBusRange {
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primary: primary_bus_num,
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secondary: secondary_bus_num,
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subordinate: secondary_bus_num,
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};
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PciePort {
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device_id,
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debug_label,
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pci_address: None,
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bus_range,
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pcie_host: None,
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pcie_cap_reg_idx: None,
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pmc_cap_reg_idx: None,
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msi_config: None,
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pmc_config: PmcConfig::new(),
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slot_control: if slot_implemented {
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Some(PCIE_SLTCTL_PIC_OFF | PCIE_SLTCTL_AIC_OFF)
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} else {
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None
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},
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slot_status: 0,
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root_control: 0,
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root_status: 0,
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hp_interrupt_pending: false,
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pme_pending_request_id: None,
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prepare_hotplug: false,
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removed_downstream_valid: false,
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}
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}
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pub fn new_from_host(pcie_host: PcieHostPort, slot_implemented: bool) -> Self {
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let bus_range = pcie_host.get_bus_range();
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PciePort {
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device_id: pcie_host.read_device_id(),
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debug_label: pcie_host.host_name(),
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pci_address: None,
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bus_range,
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pcie_host: Some(pcie_host),
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pcie_cap_reg_idx: None,
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pmc_cap_reg_idx: None,
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msi_config: None,
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pmc_config: PmcConfig::new(),
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slot_control: if slot_implemented {
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Some(PCIE_SLTCTL_PIC_OFF | PCIE_SLTCTL_AIC_OFF)
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} else {
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None
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},
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slot_status: 0,
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root_control: 0,
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root_status: 0,
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hp_interrupt_pending: false,
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pme_pending_request_id: None,
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prepare_hotplug: false,
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removed_downstream_valid: false,
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}
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}
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pub fn get_device_id(&self) -> u16 {
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self.device_id
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}
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pub fn debug_label(&self) -> String {
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self.debug_label.clone()
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}
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pub fn allocate_address(
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&mut self,
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resources: &mut SystemAllocator,
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) -> std::result::Result<PciAddress, PciDeviceError> {
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if self.pci_address.is_none() {
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match &self.pcie_host {
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Some(host) => {
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let address = PciAddress::from_str(&host.host_name())
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.map_err(|e| PciDeviceError::PciAddressParseFailure(host.host_name(), e))?;
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if resources.reserve_pci(
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Alloc::PciBar {
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bus: address.bus,
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dev: address.dev,
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func: address.func,
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bar: 0,
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},
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host.host_name(),
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) {
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self.pci_address = Some(address);
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} else {
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self.pci_address = None;
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}
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}
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None => match resources.allocate_pci(self.bus_range.primary, self.debug_label()) {
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Some(Alloc::PciBar {
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bus,
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dev,
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func,
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bar: _,
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}) => self.pci_address = Some(PciAddress { bus, dev, func }),
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_ => self.pci_address = None,
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},
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}
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}
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self.pci_address.ok_or(PciDeviceError::PciAllocationFailed)
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}
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fn read_pcie_cap(&self, offset: usize, data: &mut u32) {
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if offset == PCIE_SLTCTL_OFFSET {
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*data = ((self.slot_status as u32) << 16) | (self.get_slot_control() as u32);
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} else if offset == PCIE_ROOTCTL_OFFSET {
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*data = self.root_control as u32;
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} else if offset == PCIE_ROOTSTA_OFFSET {
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*data = self.root_status;
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}
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}
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fn write_pcie_cap(&mut self, offset: usize, data: &[u8]) {
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self.removed_downstream_valid = false;
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match offset {
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PCIE_SLTCTL_OFFSET => {
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let value = match u16::from_slice(data) {
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Some(&v) => v,
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None => {
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warn!("write SLTCTL isn't word, len: {}", data.len());
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return;
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}
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};
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// if slot is populated, power indicator is off,
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// it will detach devices
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let old_control = self.get_slot_control();
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match self.slot_control.as_mut() {
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Some(v) => *v = value,
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None => return,
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}
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if (self.slot_status & PCIE_SLTSTA_PDS != 0)
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&& (value & PCIE_SLTCTL_PIC_OFF == PCIE_SLTCTL_PIC_OFF)
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&& (old_control & PCIE_SLTCTL_PIC_OFF != PCIE_SLTCTL_PIC_OFF)
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{
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self.removed_downstream_valid = true;
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self.slot_status &= !PCIE_SLTSTA_PDS;
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self.slot_status |= PCIE_SLTSTA_PDC;
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self.trigger_hp_interrupt();
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}
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if old_control != value {
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// send Command completed events
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self.slot_status |= PCIE_SLTSTA_CC;
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self.trigger_cc_interrupt();
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}
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}
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PCIE_SLTSTA_OFFSET => {
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if self.slot_control.is_none() {
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return;
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}
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let value = match u16::from_slice(data) {
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Some(v) => *v,
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None => {
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warn!("write SLTSTA isn't word, len: {}", data.len());
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return;
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}
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};
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if value & PCIE_SLTSTA_ABP != 0 {
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self.slot_status &= !PCIE_SLTSTA_ABP;
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}
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if value & PCIE_SLTSTA_PFD != 0 {
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self.slot_status &= !PCIE_SLTSTA_PFD;
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}
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if value & PCIE_SLTSTA_PDC != 0 {
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self.slot_status &= !PCIE_SLTSTA_PDC;
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}
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if value & PCIE_SLTSTA_CC != 0 {
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self.slot_status &= !PCIE_SLTSTA_CC;
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}
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if value & PCIE_SLTSTA_DLLSC != 0 {
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self.slot_status &= !PCIE_SLTSTA_DLLSC;
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}
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}
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PCIE_ROOTCTL_OFFSET => match u16::from_slice(data) {
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Some(v) => self.root_control = *v,
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None => warn!("write root control isn't word, len: {}", data.len()),
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},
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PCIE_ROOTSTA_OFFSET => match u32::from_slice(data) {
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Some(v) => {
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if *v & PCIE_ROOTSTA_PME_STATUS != 0 {
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if let Some(request_id) = self.pme_pending_request_id {
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self.root_status &= !PCIE_ROOTSTA_PME_PENDING;
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let req_id = ((request_id.bus as u32) << 8)
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| ((request_id.dev as u32) << 3)
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| (request_id.func as u32);
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self.root_status &= !PCIE_ROOTSTA_PME_REQ_ID_MASK;
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self.root_status |= req_id;
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self.root_status |= PCIE_ROOTSTA_PME_STATUS;
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self.pme_pending_request_id = None;
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self.trigger_pme_interrupt();
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} else {
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self.root_status &= !PCIE_ROOTSTA_PME_STATUS;
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if self.hp_interrupt_pending {
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self.hp_interrupt_pending = false;
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self.trigger_hp_interrupt();
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}
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}
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}
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}
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None => warn!("write root status isn't dword, len: {}", data.len()),
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},
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_ => (),
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}
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}
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pub fn read_config(&self, reg_idx: usize, data: &mut u32) {
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if let Some(pcie_cap_reg_idx) = self.pcie_cap_reg_idx {
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if reg_idx >= pcie_cap_reg_idx && reg_idx < pcie_cap_reg_idx + (PCIE_CAP_LEN / 4) {
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let offset = (reg_idx - pcie_cap_reg_idx) * 4;
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self.read_pcie_cap(offset, data);
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}
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}
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if let Some(pmc_cap_reg_idx) = self.pmc_cap_reg_idx {
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if reg_idx == pmc_cap_reg_idx + PMC_CAP_CONTROL_STATE_OFFSET {
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self.pmc_config.read(data);
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}
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}
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if let Some(host) = &self.pcie_host {
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host.read_config(reg_idx, data);
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}
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}
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pub fn write_config(&mut self, reg_idx: usize, offset: u64, data: &[u8]) {
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if let Some(pcie_cap_reg_idx) = self.pcie_cap_reg_idx {
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if reg_idx >= pcie_cap_reg_idx && reg_idx < pcie_cap_reg_idx + (PCIE_CAP_LEN / 4) {
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let delta = ((reg_idx - pcie_cap_reg_idx) * 4) + offset as usize;
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self.write_pcie_cap(delta, data);
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}
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}
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if let Some(pmc_cap_reg_idx) = self.pmc_cap_reg_idx {
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if reg_idx == pmc_cap_reg_idx + PMC_CAP_CONTROL_STATE_OFFSET {
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let old_status = self.pmc_config.get_power_status();
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self.pmc_config.write(offset, data);
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let new_status = self.pmc_config.get_power_status();
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if old_status == PciDevicePower::D3
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&& new_status == PciDevicePower::D0
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&& self.prepare_hotplug
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{
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if let Some(host) = self.pcie_host.as_mut() {
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host.hotplug_probe();
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self.prepare_hotplug = false;
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}
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}
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}
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}
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if let Some(host) = self.pcie_host.as_mut() {
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host.write_config(reg_idx, offset, data);
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}
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}
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pub fn set_capability_reg_idx(&mut self, id: PciCapabilityID, reg_idx: usize) {
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match id {
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PciCapabilityID::PciExpress => self.pcie_cap_reg_idx = Some(reg_idx),
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PciCapabilityID::PowerManagement => self.pmc_cap_reg_idx = Some(reg_idx),
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_ => (),
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}
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}
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pub fn get_bus_range(&self) -> Option<PciBridgeBusRange> {
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Some(self.bus_range)
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}
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pub fn get_bridge_window_size(&self) -> (u64, u64) {
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if let Some(host) = &self.pcie_host {
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host.get_bridge_window_size()
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} else {
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(PCIE_BR_MEM_SIZE, PCIE_BR_PREF_MEM_SIZE)
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}
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}
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fn get_slot_control(&self) -> u16 {
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if let Some(slot_control) = self.slot_control {
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return slot_control;
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}
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0
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}
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pub fn clone_interrupt(&mut self, msi_config: Arc<Mutex<MsiConfig>>) {
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self.msi_config = Some(msi_config);
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}
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pub fn hotplug_implemented(&self) -> bool {
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self.slot_control.is_some()
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}
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fn trigger_interrupt(&self) {
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if let Some(msi_config) = &self.msi_config {
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let msi_config = msi_config.lock();
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if msi_config.is_msi_enabled() {
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msi_config.trigger()
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}
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}
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}
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fn trigger_cc_interrupt(&self) {
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if (self.get_slot_control() & PCIE_SLTCTL_CCIE) != 0
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&& (self.slot_status & PCIE_SLTSTA_CC) != 0
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{
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self.trigger_interrupt()
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}
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}
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fn trigger_hp_interrupt(&self) {
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let slot_control = self.get_slot_control();
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if (slot_control & PCIE_SLTCTL_HPIE) != 0
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&& (self.slot_status & slot_control & (PCIE_SLTCTL_ABPE | PCIE_SLTCTL_PDCE)) != 0
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{
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self.trigger_interrupt()
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}
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}
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fn trigger_pme_interrupt(&self) {
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if (self.root_control & PCIE_ROOTCTL_PME_ENABLE) != 0
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&& (self.root_status & PCIE_ROOTSTA_PME_STATUS) != 0
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{
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self.trigger_interrupt()
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}
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}
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pub fn inject_pme(&mut self) {
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if (self.root_status & PCIE_ROOTSTA_PME_STATUS) != 0 {
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self.root_status |= PCIE_ROOTSTA_PME_PENDING;
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self.pme_pending_request_id = self.pci_address;
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} else {
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let request_id = self.pci_address.unwrap();
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let req_id = ((request_id.bus as u32) << 8)
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| ((request_id.dev as u32) << 3)
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| (request_id.func as u32);
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self.root_status &= !PCIE_ROOTSTA_PME_REQ_ID_MASK;
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self.root_status |= req_id;
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self.pme_pending_request_id = None;
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self.root_status |= PCIE_ROOTSTA_PME_STATUS;
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self.trigger_pme_interrupt();
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}
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}
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pub fn trigger_hp_or_pme_interrupt(&mut self) {
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if self.pmc_config.should_trigger_pme() {
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self.hp_interrupt_pending = true;
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self.inject_pme();
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} else {
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self.trigger_hp_interrupt();
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}
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}
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pub fn is_host(&self) -> bool {
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self.pcie_host.is_some()
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}
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pub fn hot_unplug(&mut self) {
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if let Some(host) = self.pcie_host.as_mut() {
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host.hot_unplug()
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}
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}
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pub fn is_match(&self, host_addr: PciAddress) -> Option<u8> {
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let _ = self.slot_control?;
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if (host_addr.bus >= self.bus_range.secondary
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&& host_addr.bus <= self.bus_range.subordinate)
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|| self.pcie_host.is_none()
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{
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Some(self.bus_range.secondary)
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} else {
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None
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}
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}
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pub fn removed_downstream_valid(&self) -> bool {
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self.removed_downstream_valid
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}
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pub fn set_slot_status(&mut self, flag: u16) {
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self.slot_status |= flag;
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}
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pub fn should_trigger_pme(&mut self) -> bool {
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self.pmc_config.should_trigger_pme()
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}
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pub fn prepare_hotplug(&mut self) {
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self.prepare_hotplug = true;
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}
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}
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