Enable most of modules under `irqchip` as well as `tsc` to work with
windows since all their dependencies have been completed. They were
already working for unix.
The test `irqchip::userspace::tests::irq_event_tokens` fails on wine,
however, it work on windows and unix natively.
The test `tsc::calibrate::tests::test_frequency_higher_than_u32` fails
for hosts with cpu>64, since the windows implementation for setting
thread affinity does not support cpu>64.
BUG=b:237024070
TEST=Ran `tools/run_tests --target=host --arch=win64`
Change-Id: I15d8f3c3256e89f89efbe64dbe2ad809fcd90a72
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3737456
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: Vaibhav Nagarnaik <vnagarnaik@google.com>
Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
Reviewed-by: Noah Gold <nkgold@google.com>
Also remove `dead_code` annotation from `apic.rs` since the consumers
have been added.
BUG=b:213149158
TEST=Ran `cargo test -p devices irqchip -- --nocapture`
Change-Id: Ifda216e23f52ce05b5fee7e80a0751cb3524cf1f
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3722189
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
Commit-Queue: Vaibhav Nagarnaik <vnagarnaik@google.com>
Implement `WhpxSplitIrqChip` for `whpx` (Hyper-V) which has a split IRQ
chip architecture. Add dependencies for the root `whpx` feature on the
`devices/whpx` feature set.
BUG=b:213149158
TEST=Compiled on windows.
Change-Id: I3b0aec441b5abdff3f0266a9467380b0cdc4fdee
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3717187
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
Commit-Queue: Vaibhav Nagarnaik <vnagarnaik@google.com>
Rather than having a global CPUIDS variable that is used by all tests
for the TSC CPUID code, we can pass a function pointer to the
tsc_frequency_cpuid() function to retrieve a specified CPUID value. For
normal use, we provide a host_cpuid_count function that uses the normal
__cpuid_count intrinsic as before. For the tests, we provide a fake
CPUID function that returns the desired test values.
This removes the potential for problems when running multiple tests in
parallel (which was hypothetical, since we only had one test so far, but
worth fixing).
BUG=b:234508273
TEST=cargo test -p devices tsc
Change-Id: Ic963b21f09f8e8d7665386ad134ae5e242b3051d
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3707623
Reviewed-by: Noah Gold <nkgold@google.com>
Commit-Queue: Daniel Verkamp <dverkamp@chromium.org>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Vaibhav Nagarnaik <vnagarnaik@google.com>
This irqchip is currently used with Haxm which doesn't implement a local
APIC.
BUG=b:213149158
TEST=Compiled.
Change-Id: I3088ea5cad68451230dc3d5f8b649d54e83b938b
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3701442
Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
Commit-Queue: Vaibhav Nagarnaik <vnagarnaik@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This allows irq processing thread to log statistics and metrics and
track them using the source of the device. To be upstreamed later.
Introduce `PCI_VENDOR_ID_CROSVM` which identifies devices created by
crosvm. And introduce `CrosvmDeviceId` which adds a unique device ID for
each type of crosvm device.
BUG=b:213149158
BUG=b:213152505
TEST=Compiled.
Change-Id: Ica1374d8a2d8fd627c9397553bb7fb62baeaff7d
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3687418
Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: Vaibhav Nagarnaik <vnagarnaik@google.com>
The AddressRange type is used for representing contiguous memory or I/O
address ranges, mostly equivalent to RangeInclusive<u64> but with the
added benefit of implementing Copy and not carrying an extra field used
only for iteration, which we don't need.
Using an inclusive range means we can represent the full address space
with no weird corner cases around the upper limit of the range (for
example, an AddressRange covering the full 64-bit space can be
represented as start: 0, end: u64::MAX).
AddressRange also replaces the previous MemRegion type, which was a
start/size pair.
This normalizes the interface of the resources crates to use
AddressRange rather than a start/size pair; more cleanups throughout the
tree may be possible, but this commit attempts to be somewhat smaller to
have a hope of being reviewable.
BUG=b:222769529
TEST=tools/presubmit --all
TEST=cargo test -p resources
Change-Id: I8c90bdc28456221b5107ef7e589233315ea739c3
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3696671
Reviewed-by: Junichi Uekawa <uekawa@chromium.org>
Reviewed-by: David Stevens <stevensd@chromium.org>
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: Daniel Verkamp <dverkamp@chromium.org>
This APIC is used by the userspace irqchip (to be upstreamed soon).
Original author: Steven Richman <srichman@google.com>
BUG=213152505
TEST=builds
Change-Id: I51b89e96af88f2f1c08998b70053fc37bd3cfcaf
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3696535
Commit-Queue: Noah Gold <nkgold@google.com>
Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
Tested-by: kokoro <noreply+kokoro@google.com>
This function is used to generate cpuid leaf 15H in some situations.
BUG=213152505
TEST=builds
Change-Id: Ia5a7c46b32f1bdba366a500caa650edb2e3ae99f
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3696534
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
Commit-Queue: Noah Gold <nkgold@google.com>
The new specialized functions take IrqEdgeEvent and IrqLevelEvent
arguments, so that callers can use them directly.
BUG=None
TEST=./tools/presubmit
Change-Id: I2c1272e31f6b20eb22743b003bd23b9c1105cda6
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3548066
Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: Dmitry Torokhov <dtor@chromium.org>
The files include
- coiommu.rs
- msix.rs
- pci_configuration.rs
- pci_root.rs
- pci_bridge.rs
- pvpanic.rs
- stub.rs
Rest of the changes in the patch are supporting changes to build
and test.
Test: presubmit
Bug: b:213149278
Change-Id: Ic8fbcda4ad95370689b232c1656e782ee33425e1
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3541336
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
Commit-Queue: Vikram Auradkar <auradkar@google.com>
Upstreams support for Tubes on Windows, splitting Tube into platform
specific files. This contains several critical enhancements:
* POSIX Tubes support multi producer multi consumer configurations, but
Windows has remained strictly SPSC for each direction. Windows cannot
support MPMC, and that configuration is not really something we want
either. To address that, this CL introduces directional Tubes. A
SendTube is clonable, and a RecvTube is not, which gives us MPSC.
* This CL also fixes multiple interface conflicts that have developed
between Linux & Windows:
+ send wasn't async on the Linux AsyncTube.
+ send data wasn't passed as owned on the Linux AsyncTube.
+ Adds the 'static constraint for AsyncTube::send on POSIX. This is an
requirement on Windows.
+ Event::read_timeout doesn't need to take &mut self, and it wasn't
downstream. This CL switches to &self.
* Adds the missing notifier.rs file in base.
Note that this CL does not attempt to remove balloon's usage of
Tube::try_clone. That's a somewhat involved issue that should be tackled in
its own CL.
Test: tested downstream on Windows & Linux bots, upstream on Linux bots.
Bug: b:221484449
Change-Id: I288dbc1d1e42f8ce08258cdaaf85100ca93721ef
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3536897
Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: Noah Gold <nkgold@google.com>
Linux expects that PCI bars lie within a compatible bridge window, which
are typically specified via _CRS objects in ACPI. This change adds an
option to restrict mmio allocations (i.e. PCI bars) to within a
specified set of ranges. The specified set of ranges is intersected with
the default mmio allocation ranges generated by the crosvm arch code to
produce the final mmio allocation ranges.
This change is required to remove pci=nocrs from the CrOS guest's kernel
command line flags. Removing that flag is a prerequisite for enabling
virtio-iommu, since without the configuration information from ACPI, the
kernel reserves all IOVAs in iova_reserve_pci_windows.
BUG=b:181736020
TEST=boot manatee w/o pci=nocrs kernel cmdline flag
TEST=tast run trogdor|hatch arc.Boot.vm
Change-Id: I0a096420c5d5ef56dd76021951968e264ce40f42
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3499900
Reviewed-by: Junichi Uekawa <uekawa@chromium.org>
Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: David Stevens <stevensd@chromium.org>
Remove the ramoops region from high_mmio when constructing the system
allocator. This means the aarch64 code no longer needs to manually
adjust high_mmio when determining the pci regions.
BUG=b:181736020
TEST=Check arcvm pstore still works
Change-Id: I81ca398a1984f0efb30c0a4d4b620bd50fe9df85
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3516667
Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: David Stevens <stevensd@chromium.org>
In order to avoid deadlocks (when a Vcpu thread has locked the ioapic and
the ioapic sends a AddMsiRoute signal to the main thread which itself may
be busy trying to call service_irq) KvmSplitIrqChip defers IRQs by using
vector of delayed IRQs and queuing it up for the next main thread loop
spin.
The problem is that next loop spin will ever happen if there will be
any *unrelated* trigger event to be serviced which means IRQ reinjection
may take really long time, at least longer than some devices may assume
before timeout.
Instead of relaying on non-deterministic mechanism, make sure the next
trigger event for main thread is around the corner by:
- adding a new event - strictly related to processing delayed IRQs
- adding a new token type in main thread and correlate the new event
occurrence with process_delayed_irq_events() irqchip call
- writing to the new event as soon as new IRQ is added to the delayed
vector
This makes sure that delayed IRQs (if present) are always on main loop's
TODO list.
BUG=b:184871003
TEST=boot guest using crosvm --split-irqchip flag and check if IOAPIC
related IRQs are working
Change-Id: I89e731f19a7fa5215cd4a57fa5c94a89a7c9161a
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3494286
Reviewed-by: Colin Downs-Razouk <colindr@google.com>
Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: Tomasz Nowicki <tnowicki@google.com>
In order to emulate IOAPIC pins and still be able to inject IRQs
via KVM eventfd, SplitIrqChip driver allocates input and output eventfd
for each pin:
- the input eventfd listens for incoming events (e.g. physical IRQ
occurrence or userspace emulated IRQ). This gives chance to to emulate
pin states before handing over to KVM
- the output eventfd inject the actual virtual IRQ in KVM standard manner
Once the guest tries to configure a new IOAPIC pin, the output event GSI
number is allocated dynamically. So there is no chance to know GSI number
upfront to expose it via e.g. ACPI. This is the blocker for direct IRQ
forwarding where 1:1 mapping is inherent feature.
Allocate output eventfd vector and fill in with 1:1 GSI mapping upfront
only for direct configuration feature. Any potential guest IOAPIC pin
configuration request will used pre-allocated GSI number so that guest
will see proper IRQ number. No functional changes for the rest of the cases.
BUG=b:184871003
TEST=boot guest using crosvm --split-irqchip flag and check if IOAPIC
related IRQs are working
Change-Id: Ie1578a831ff21489e4e7dd9c7ec3f5384b4af16a
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3494285
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
Reviewed-by: Steven Richman <srichman@google.com>
Commit-Queue: Tomasz Nowicki <tnowicki@google.com>
This reverts commit d2d66bc0a4.
Reason for revert: It turns out that adding the first page to the pool
of memory managed by the MMIO allocator has undesired consequences
since crosvm will actually use it for MMIO regions. The first page
has special semantics in other code though, and thus we get stray
accesses to this region, with hard-to-predict consequences.
BUG=b:188011323
TEST=cq
Original change's description:
> system_allocator: allow more than one region to be in the pool
>
> Allows crosvm-direct to have 0-0xfff regions to be mapped.
>
> limitations: Only the first regions gets reflected in the
> pool_base/pool_size.
>
> BUG=b:188011323
> BUG=b:184815519
> TEST=build
>
> Change-Id: I9da3cb2b8d5611068f9323d6ebf62f44162838b4
> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3450017
> Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
> Tested-by: kokoro <noreply+kokoro@google.com>
> Commit-Queue: Junichi Uekawa <uekawa@chromium.org>
Bug: b:188011323
Bug: b:184815519
Change-Id: Ib42b3007662a7a49ad876b83a01f1bb88d09d5f7
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3497136
Reviewed-by: Keiichi Watanabe <keiichiw@chromium.org>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Mattias Nissler <mnissler@chromium.org>
Commit-Queue: Mattias Nissler <mnissler@chromium.org>
io ports is a 16 bit thing, check that it is actually 16 bits and fix
the parameters.
BUG=None
TEST=read intel SDM, run crosvm test
Change-Id: I50b6d5593b0699317ac2f852836208a46240714b
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3470601
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
Commit-Queue: Junichi Uekawa <uekawa@chromium.org>
Some tests had unrealistic values, fix them in case I want to add some
validation in the future.
BUG=None
TEST=None
Change-Id: I126c83b4ac91442f87aae8be9e84565a7a3d98a2
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3446980
Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Noah Gold <nkgold@google.com>
Commit-Queue: Junichi Uekawa <uekawa@chromium.org>
Allows crosvm-direct to have 0-0xfff regions to be mapped.
limitations: Only the first regions gets reflected in the
pool_base/pool_size.
BUG=b:188011323
BUG=b:184815519
TEST=build
Change-Id: I9da3cb2b8d5611068f9323d6ebf62f44162838b4
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3450017
Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: Junichi Uekawa <uekawa@chromium.org>
The previous limit was incorrect, as we are using SPI (Shared Peripheral
Interrupt) type interrupt sources for PCI devices, but the limit was
based on the total number of SPI + PPI interrupts.
This fixes interrupt delivery when many PCI devices are used on arm
platforms.
BUG=b:218757314
TEST=Run crosvm with 32+ block devices on trogdor
Change-Id: Ie89bc5b7115117d8acaca30ff758b9342940b450
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3453119
Reviewed-by: Dmitry Torokhov <dtor@chromium.org>
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: Daniel Verkamp <dverkamp@chromium.org>
In preparation to allow multiple low memory regions to be passed on, I wanted to
make initialization simpler.
Introduce `MemRegion` struct instead of tuple to help me understand it is a base
and size.
BUG=b:188011323
TEST=build
Change-Id: Ie8b54354a25c478d5ad0a0185b7e07d28840dd87
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3439666
Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: Junichi Uekawa <uekawa@chromium.org>
It's a simple enum, so it should be Copy.
TEST=tools/dev_container tools/run_tests
TEST=tools/dev_container tools/run_tests --target=vm:aarch64
Change-Id: Ieeacedb10fa6a93d6cdd9878097c66aa936f8e30
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3420329
Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: Andrew Walbran <qwandor@google.com>
This involves two main changes:
* Protected VMs must be created with KVM_VM_TYPE_ARM_PROTECTED.
* pVM firmware is now loaded by IPA rather than memslot ID.
There are also a lot of trivial changes because the ProtectionType enum
was moved from the devices crate to the hypervisor crate.
BUG=b:209794844
TEST=Will tested manually with patched kernel and dummy firmware
Change-Id: I1dd75e20063ca4736f155292ca5f70b94664fdd9
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3330204
Auto-Submit: Andrew Walbran <qwandor@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
Commit-Queue: Daniel Verkamp <dverkamp@chromium.org>
With vfio pci device hotplug, bus->devices will be inserted and removed at
runtime in different vcpu threads, so mutex should be used to protect it.
Both each vcpu thread and pci_root share mmio_bus and io_bus, so use Arc
for mmio_bus and io_bus. But pci_root is inserted into io_bus for pci cfg io,
in order to resolve reference loop and memory leak, weak is used for
pci_root.mmio_bus and pci_root.io_bus.
BUG=b:174705596
TEST=boot a vm and check its function
Change-Id: I7b3e63db76a90bc3873619b4d80a66db741ce78f
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3184724
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: Chirantan Ekbote <chirantan@chromium.org>
Reviewed-by: Chirantan Ekbote <chirantan@chromium.org>
Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
Pull the duplicated first statement out of the IRQ triggering sequences
to placate clippy's new warning.
BUG=b:197251702
TEST=bin/clippy # with rust-toolchain = 1.54.0
Change-Id: I8cd8577af35990522e198f97f3a666ad6730e31b
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3108614
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: Daniel Verkamp <dverkamp@chromium.org>
Reviewed-by: Allen Webb <allenwebb@google.com>
Reviewed-by: Colin Downs-Razouk <colindr@google.com>
Instead of checking each item for Some/Ok-ness, filter down to just the
desired items using flatten() on the iterator.
BUG=b:197251702
TEST=bin/clippy # with rust-toolchain = 1.54.0
Change-Id: I80db12c36f41e76f5dff6c30299a3f5d3745f578
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3108613
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: Daniel Verkamp <dverkamp@chromium.org>
Reviewed-by: Allen Webb <allenwebb@google.com>
This reverts commit e470ef9933.
Reason for revert: possibly breaks critical test, in turn CQ.
Original change's description:
> devices: irqchip: add need_halted function
>
> This allows irqchip implementations to specify whether they need to be
> notified via the halted() function when the vCPU encounters a HLT
> instruction.
>
> All of the current in-tree irqchip implementations do nothing on
> halted(), so this will always return false for now, but a fully
> userspace irqchip would need these notifications.
>
> Querying this function will allow the hypervisor code to determine
> whether disabling VM exits on HLT instructions is allowed.
>
> BUG=b:181106085
> TEST=test_all
>
> Change-Id: I433fe208d125dcd14e7100ce5aff37474b423a83
> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/2937304
> Reviewed-by: Colin Downs-Razouk <colindr@google.com>
> Reviewed-by: Zach Reizner <zachr@chromium.org>
> Tested-by: kokoro <noreply+kokoro@google.com>
> Commit-Queue: Daniel Verkamp <dverkamp@chromium.org>
Bug: b:181106085
BUG=b:194452080
Change-Id: I755fc732e79a56f0306819e23ba9bd6c840dc927
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3045583
Commit-Queue: Leo Lai <cylai@google.com>
Commit-Queue: Rubber Stamper <rubber-stamper@appspot.gserviceaccount.com>
Owners-Override: Leo Lai <cylai@google.com>
Auto-Submit: Leo Lai <cylai@google.com>
Bot-Commit: Rubber Stamper <rubber-stamper@appspot.gserviceaccount.com>
This allows irqchip implementations to specify whether they need to be
notified via the halted() function when the vCPU encounters a HLT
instruction.
All of the current in-tree irqchip implementations do nothing on
halted(), so this will always return false for now, but a fully
userspace irqchip would need these notifications.
Querying this function will allow the hypervisor code to determine
whether disabling VM exits on HLT instructions is allowed.
BUG=b:181106085
TEST=test_all
Change-Id: I433fe208d125dcd14e7100ce5aff37474b423a83
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/2937304
Reviewed-by: Colin Downs-Razouk <colindr@google.com>
Reviewed-by: Zach Reizner <zachr@chromium.org>
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: Daniel Verkamp <dverkamp@chromium.org>
Replace an else block that just returns None with the equivalent use of
the question mark operator, and rewrite the comment that used to be in
the else block to match.
Fixes the clippy warning "this if-let-else may be rewritten with the `?`
operator".
https://rust-lang.github.io/rust-clippy/master/index.html#question_mark
BUG=None
TEST=bin/clippy
TEST=cargo test -p devices
Change-Id: Ifda6d55c16e12fc7939343757d7f2843b4df9b27
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/2885784
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: Daniel Verkamp <dverkamp@chromium.org>
Reviewed-by: Tomasz Jeznach <tjeznach@chromium.org>
Fixes clippy warnings like:
using `clone` on type `...` which implements the `Copy` trait
and
redundant clone
note: this value is dropped without further use
BUG=None
TEST=bin/clippy
TEST=cargo test -p devices
Change-Id: I8c13b79b54265e5527cadcb8a2e9f54419044bcf
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/2885781
Reviewed-by: Dylan Reid <dgreid@chromium.org>
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: Daniel Verkamp <dverkamp@chromium.org>
Enable support for runtime verification of number
of irqchip kernel emulated inputs, up to 120 pins.
KVM implementation supporting extended input pins shall
report KVM_CHECK_EXTENSION/KVM_CAP_IOAPIC_NUM_PINS value.
BUG=b:179648314
TEST=On systems with 24/120 pin IOAPIC kvm emulation.
Change-Id: I80063216310e427d664e3eaca3aba27e8a972cde
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/2893366
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: Tomasz Jeznach <tjeznach@chromium.org>
Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
These parameters multiplied the number of type arguments to build_vm
unnecessarily and complicated the thread of execution in the programmers
head. Closures also complicate the borrow rules, making things much
harder to change.
This change uses the results of the closures (e.g. PCI devices, IRQ
chips) as parameters instead. The rest of this change follows naturally
from pulling on that thread until tests pass.
As a result of the removal of several type arguments, the code size was
reduced by ~100KiB on a 5MiB build.
BUG=b:185170486
TEST=./test_all
Change-Id: I6bcc5eb1b1f3031d4328bb4a81ddef618d04767b
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/2829136
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: Zach Reizner <zachr@chromium.org>
Reviewed-by: Tomasz Jeznach <tjeznach@chromium.org>
Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
Some judgement calls were made about unnecessary wrapping. Usually they
would get resolved by removing the wrapping or returning a convenient
error, but the ones that returned results for consistency with other
functions were added to the allow list.
The error handling in the usb code had a lot of unit error types which
is now a clippy lint. This was resolved by either removing the result
entirely or returning a convenient error.
The field_reassign_with_default lint is faulty and was added to the list
of supressions. This affected virtio-wayland code.
BUG=b:179277332
TEST=cargo clippy with rustc 1.50+
Change-Id: Ie812cdeaf7c42f4f2b47b1dc87f05a7c87a60f8f
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/2757510
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Zach Reizner <zachr@chromium.org>
Reviewed-by: Gurchetan Singh <gurchetansingh@chromium.org>
Auto-Submit: Zach Reizner <zachr@chromium.org>
Commit-Queue: Dennis Kempin <denniskempin@google.com>
More recent Intel IO-APICs can support more than 24 interrupt
lines. This change enables variable size of IO-APIC lines for
user level IO-APIC emulation code (split-irqchip).
Reported version and supported IO-APIC registes matching ICH10
implementation of IO-APIC device.
BUG=b:181795297
TEST=boot and allocate irq from upper range.
Change-Id: I56480befb39c4c268266f04e4a93105402248772
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/2733579
Tested-by: Tomasz Jeznach <tjeznach@chromium.org>
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: Tomasz Jeznach <tjeznach@chromium.org>
Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
rutabaga_gralloc is a cross-platform, Rust-based buffer
manager.
The rationale for this change is:
1) For the {cross-domain, wayland} context type, we need to
have a good story for the crucial "wl-dmabuf" feature. As
minigbm has been thoroughly tested on ChromeOS and currently
powers the "wl-dmabuf" feature, it only makes sense for us to
have a path to minigbm for the cross-domain prototype. This
will be used by Sommelier.
2) While minigbm allocation works well on Chromebooks, it is
not sufficient for cross-platform purposes. For their Virtual
Graphics Interface (VGI) initiative, Android graphics
virtualization experts have expressed their desire for a Vulkan
based allocator. This will to go alongside cros_gralloc in
minigbm, which is considered by many to be the ""world's
premiere gralloc implementation".
3) Android graphics virtualization experts have expressed their
desire for vkMapMemory(..) to be used when crosvm is in
multi-process mode. Currently, only dma-buf mmap() is supported
for zero-copy blobs in multi-process mode. dma-buf mmap() is not
guaranteed to work on Nvidia (a "must have" for Cuttlefish) or
any other driver for that matter (we *make* it work for ChromeOS).
Possibly only solution: vkMapMemory ;-)
With these goals in mind, here's a summary of the revelant changes:
* Renamed the {gpu_allocator.rs, GpuMemoryAllocator trait} to be
{gralloc.rs, Gralloc trait}.
* Moved all GPU allocation out of the resources crate and into
the rutabaga_gfx crate. This will allow the resources crate to
be focused on managing resources for virtual machines.
* Moved the gpu_buffer crate into the gralloc module in the
rutabaga_gfx crate. The same functionality is now under
"minigbm.rs", "minigbm_bindings.rs" and "rendernode.rs"
* Added an optional dependency on vulkano.rs. vulkano.rs is a safe
Rust wrapper around the Vulkan api [a]. It's emphasis on type
safety makes a good fit for crosvm, though there are other high
quality crates out there (gfx-rs, ash.rs). Though development
has slowed down, it should satisfy goals (2) and (3) quite easily.
* Added a system_gralloc implementation based on memfd. This can be
used when minigbm or Vulkano features are not used, to replicate the
highly useful "wl-shm" feature in Sommelier. Astute observers will
note this can also enable seamless Wayland windowing without GPU
features for Android too. Some minor changes to the base crate were
needed.
* Cut down on the amount of DrmFormats to the subset needed by
Sommelier and cros_gralloc.
* Moved checked arithmetic into it's own file.
* Internally renamed to "wl-dmabuf" feature to be the "minigbm"
feature. This is because "wl-dmabuf" has a dependency on minigbm.
* Small rutabaga_gfx cleanups
[a] https://github.com/vulkano-rs/vulkano/blob/master/DESIGN.md
BUG=b:146066070, b:173630595, b:150239451
TEST=launch virtual machine with 2D mode
TEST=launch virtual machine with 3D mode
TEST=run sommelier with "wl-dmabuf" and "wl-shm"
Change-Id: I693a39cef64cd98e56d843d3c60caa7983d4d6e1
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/2626487
Tested-by: Gurchetan Singh <gurchetansingh@chromium.org>
Reviewed-by: Zach Reizner <zachr@chromium.org>
Commit-Queue: Gurchetan Singh <gurchetansingh@chromium.org>
Allow devices to be added to a Bus without a mutex. If a device
implements BusDeviceSync and is inserted into the Bus via the new
insert_sync function, the Bus will not lock the device before write and
read operations. This feature will allow IrqChip implementations to use
the mmio bus for APIC mmio, and allow each vcpu to write to their
respective APICs simultaneously.
This also changes the BusDevice trait so read and write functions take a
new BusAccessInfo struct. The BusAccessInfo conveys the full address of
the read/write operation, the offset of the address relative to the
device start address, and an id that in practice will hold the vcpu id
for the vcpu thread perforing the read/write.
As a result, inserts into the Bus are no longer distinguished between
full_addr and non full_addr inserts. Instead, each device's BusDevice
implementation must decide whether they use the absolute read/write
address or the relative read/write offset.
BUG=chromium:1077058
TEST=ran build_test
TEST=ran simple debian image
Change-Id: I9125aaa69869c1004b6c6a099b50f5c58038d4ab
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/2514662
Reviewed-by: Zach Reizner <zachr@chromium.org>
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: Colin Downs-Razouk <colindr@google.com>
Add methods to the IrqChip trait to block in userspace on halted vcpus.
Add IrqChip::check_capability, used for cpuid setup.
Move interrupt injection logic from linux.rs to a new
IrqChip::inject_interrupts method, which replaces interrupt_requested
and get_external_interrupt.
These changes are to support setup, run loop, and injection in the
userspace irqchip.
BUG=chromium:1077058
TEST=boots with KVM kernel irqchip, KVM split irqchip
Change-Id: I8f46b5edf36acc485b5f76e7aed3e71c3b984c0e
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/2419674
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: Colin Downs-Razouk <colindr@google.com>
Reviewed-by: Keiichi Watanabe <keiichiw@chromium.org>
Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
Previously the caller of ioapic::new was responsible for calling
register_irq_event on the IOAPIC's outgoing events. The MSI IrqRoutes
for these outgoing events used the same GSIs < 24 as the incoming
PIC/IOAPIC routes.
This worked for the split irqchip, because PIC/IOAPIC events are handled
in userspace and MSI events in the kernel, so there was no confusion
about which route an event should use. But with the userspace irqchip,
the routes have to be differentiated, otherwise incoming and outgoing
IOAPIC events with the same GSI trigger each other in a loop. Also,
registering all outgoing IOAPIC events upfront increased the number of
irq event tokens by 24, even though only a few outgoing events are used.
Now the IOAPIC is responsible for registering outgoing events and it
allocates new GSIs >= 24 for its MSI routes. An event and route are
only set up when a redirection table entry is configured with non-zero
MSI data.
BUG=chromium:1077058
TES=boots with split irqchip
Change-Id: I87c1df6150d50205810759ef152e1c9b33bcfe4d
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/2419672
Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: Colin Downs-Razouk <colindr@google.com>
There were some assumptions built into the hypervisor abstraction
implementations that we would only ever be registering a single Event
for any irq number, but that is no longer the case since 1d0f160. So
this change updates the hypervisor abstraction trait functions to allow
callers of irq_event_tokens to distinguish between multiple events that
refer to the same irq number using an IrqEventIndex. This index is then
used when calling service_irq_event.
Also, if register_irq_event would add a new irq event that the main
thread should wait on, register_irq_event will return the associated
IrqEventIndex. This change also updates linux.rs to use these changes.
The --split-irqchip mode may work even without this fix, depending on
which devices are sharing irqs. If the devices using shared irqs are all
virtio pci devices they may switch to MSIx mode and then not need their
original interrupt event.
BUG=chromium:1077058
TEST=disabled MSI mode on pci devices, forced additional irq sharing,
and verified that --split-irqchip mode still works + cargo test -p
devices
Change-Id: I4feb2817b6c477284ad463c0221d1f156813b6ce
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/2405300
Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: Colin Downs-Razouk <colindr@google.com>
This is a layer above PollContext with a more generic interface.
As PollContext is used so widely, this is quite a large change
in order to accomodate the interface update, especially with the
use of RawDescriptor. In some cases this has caused an echo
of updates to RawDescriptor, which is fine because of our eventual
goal to move the whole codebase to it regardless.
Note there are a few instances of forcing the RawDescriptor update
chain to stop, ex. ioctl. This is to keep the scope of this CL
concentrated and avoid changing entire other areas.
Note that this CL leaves out a few additional pieces of work:
- The sole usage of EpollContext over PollContext (event_loop),
which poses a bigger challenge for interface changes
- Full PollToken renaming, which is a tiny change turned difficult
due to the unavailability of type aliases for traits.
- Renaming certain methods which have been updated to use
RawDescriptor such as keep_fds. Some have enough dependencies that
they are worth avoiding to keep this CL pointed, but will be
addressed in future CLs to make sure the whole codebase is on the
fd->descriptor train
BUG=b:162363783
TEST=./build_test
Change-Id: Iff2cfe8f90dea55f1388f8e91bdc698e121a8e43
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/2455726
Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: Michael Hoyle <mikehoyle@google.com>
This allows code to create references to traits such as `&dyn Vcpu` for
`&dyn IrqChip`. This also allows keeping such traits inside of opaque
`Box` like wrappers.
To achieve this, trait methods referencing `Self` have an additonal
`where` clause that restricts them to sized types. Associated types are
removed and replaced with their trait equivalents (as parameters) or an
opaque Box (as return values).
To work around certain cases where a concrete type is needed, such as
for KVM based `IrqChip` impls, the `downcast_rs` trait is used to allow
`dynamic_cast` style casting.
The binary size impact of this change is small. For comparison, here is
the size change with this commit:
armv7a -0.49% (-9 kiB)
aarch64 -0.17% (-3 kiB)
x86_64 +1.77% (+40 KiB)
BUG=None
TEST=build_test
Cq-Depend: chromium:2466660
Change-Id: I1a408734832d2971ea2979c1bc64b2ffe051b02d
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/2439298
Reviewed-by: Zach Reizner <zachr@chromium.org>
Tested-by: Zach Reizner <zachr@chromium.org>
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: Zach Reizner <zachr@chromium.org>
Note the CL size is large entirely due to the rename,
the changes are mostly negligible.
Also making a few small additional changes in sys_util
areas that don't need much attention in base. This includes
typedefing and adding specific imports for areas that don't
require significant interface changes.
BUG=b:162363783
TEST=./build_test
Change-Id: I4a2c9c4cdce7565806ed338e241c6b8c82c855c7
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/2415180
Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: Michael Hoyle <mikehoyle@google.com>
