Jingkui Wang 2de0088c9e make aarch64 pci dma-coherent ... On arm, if the device is not coherent, guest kernel will allocate dma memory as no-cacheable. Crosvm on the host user space thinks the memory is cacheable. Thus when guest kernel write to dma memory, it will bypass the cache, crosvm won't see the change. BUG=None TEST=local build and test Change-Id: If6cf2d28afec61d5beb136628116ff9e7e0483f4 Reviewed-on: https://chromium-review.googlesource.com/1497739 Commit-Ready: Jingkui Wang <jkwang@google.com> Tested-by: Jingkui Wang <jkwang@google.com> Reviewed-by: Sonny Rao <sonnyrao@chromium.org> Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>		2019-03-03 06:01:39 -08:00
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fdt.rs	make aarch64 pci dma-coherent	2019-03-03 06:01:39 -08:00
lib.rs	error: Consistently use Display instead of error description()	2019-03-02 17:41:31 -08:00