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For nonroot vfio-pci device, its prefetchable bars will be allocated in continuous region, its nonprefetchable bars will be allocated in another continuous region. Without descending the bar's size, this allocation waste some mmio. For example, a vfio-pci device has two non prefetchable bars: bar0's size is 1M, bar2's size is 8M. without descending [bar0, bar2], it will allocate 16M mmio, 0~8M for Bar0, 8~16M for Bar2, although bar0 need 1M only, it occupy 8M to satisfy bar2's 8M alignment requirement. With descending [bar2, bar0], it will allocate 9M mmio, 0~8M for bar2, 8M ~ 9M for bar0. BUG=b:185084350 TEST=check pcie rp's bridge window in brya-manatee. Change-Id: I7d93e601f6a46cabe8896aaec065a9dba18c60fa Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3500060 Reviewed-by: Daniel Verkamp <dverkamp@chromium.org> Tested-by: kokoro <noreply+kokoro@google.com> Commit-Queue: Daniel Verkamp <dverkamp@chromium.org> |
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Cargo.toml |