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https://chromium.googlesource.com/crosvm/crosvm
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Along with this rename comes updating all usages to the appropriate RawDescriptor traits. As per usual it touches many files, but makes no significant changes. The only remaining instance of "keep_fds" is to call out to 3p lib adhd. BUG=b:162363783 TEST=./build_test Change-Id: I6d292cc6404a9f84ffa5bf1320b6545a28842afa Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/2488071 Commit-Queue: Michael Hoyle <mikehoyle@google.com> Tested-by: Michael Hoyle <mikehoyle@google.com> Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
325 lines
11 KiB
Rust
325 lines
11 KiB
Rust
// Copyright 2018 The Chromium OS Authors. All rights reserved.
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// Use of this source code is governed by a BSD-style license that can be
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// found in the LICENSE file.
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use std::convert::TryInto;
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use base::warn;
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use vm_memory::GuestAddress;
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use super::*;
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/// Contains the data for reading and writing the common configuration structure of a virtio PCI
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/// device.
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///
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/// * Registers:
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/// ** About the whole device.
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/// le32 device_feature_select; // read-write
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/// le32 device_feature; // read-only for driver
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/// le32 driver_feature_select; // read-write
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/// le32 driver_feature; // read-write
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/// le16 msix_config; // read-write
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/// le16 num_queues; // read-only for driver
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/// u8 device_status; // read-write (driver_status)
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/// u8 config_generation; // read-only for driver
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/// ** About a specific virtqueue.
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/// le16 queue_select; // read-write
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/// le16 queue_size; // read-write, power of 2, or 0.
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/// le16 queue_msix_vector; // read-write
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/// le16 queue_enable; // read-write (Ready)
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/// le16 queue_notify_off; // read-only for driver
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/// le64 queue_desc; // read-write
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/// le64 queue_avail; // read-write
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/// le64 queue_used; // read-write
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pub struct VirtioPciCommonConfig {
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pub driver_status: u8,
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pub config_generation: u8,
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pub device_feature_select: u32,
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pub driver_feature_select: u32,
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pub queue_select: u16,
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pub msix_config: u16,
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}
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impl VirtioPciCommonConfig {
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pub fn read(
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&mut self,
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offset: u64,
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data: &mut [u8],
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queues: &mut [Queue],
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device: &mut dyn VirtioDevice,
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) {
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match data.len() {
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1 => {
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let v = self.read_common_config_byte(offset);
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data[0] = v;
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}
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2 => {
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let v = self.read_common_config_word(offset, queues);
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data.copy_from_slice(&v.to_le_bytes());
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}
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4 => {
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let v = self.read_common_config_dword(offset, device);
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data.copy_from_slice(&v.to_le_bytes());
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}
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8 => {
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let v = self.read_common_config_qword(offset);
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data.copy_from_slice(&v.to_le_bytes());
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}
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_ => (),
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}
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}
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pub fn write(
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&mut self,
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offset: u64,
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data: &[u8],
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queues: &mut [Queue],
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device: &mut dyn VirtioDevice,
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) {
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match data.len() {
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1 => self.write_common_config_byte(offset, data[0]),
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2 => self.write_common_config_word(
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offset,
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// This unwrap (and those below) cannot fail since data.len() is checked.
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u16::from_le_bytes(data.try_into().unwrap()),
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queues,
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),
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4 => self.write_common_config_dword(
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offset,
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u32::from_le_bytes(data.try_into().unwrap()),
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queues,
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device,
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),
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8 => self.write_common_config_qword(
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offset,
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u64::from_le_bytes(data.try_into().unwrap()),
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queues,
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),
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_ => (),
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}
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}
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fn read_common_config_byte(&self, offset: u64) -> u8 {
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// The driver is only allowed to do aligned, properly sized access.
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match offset {
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0x14 => self.driver_status,
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0x15 => self.config_generation,
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_ => 0,
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}
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}
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fn write_common_config_byte(&mut self, offset: u64, value: u8) {
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match offset {
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0x14 => self.driver_status = value,
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_ => {
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warn!("invalid virtio config byt access: 0x{:x}", offset);
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}
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}
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}
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fn read_common_config_word(&self, offset: u64, queues: &[Queue]) -> u16 {
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match offset {
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0x10 => self.msix_config,
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0x12 => queues.len() as u16, // num_queues
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0x16 => self.queue_select,
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0x18 => self.with_queue(queues, |q| q.size).unwrap_or(0),
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0x1a => self.with_queue(queues, |q| q.vector).unwrap_or(0),
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0x1c => {
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if self.with_queue(queues, |q| q.ready).unwrap_or(false) {
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1
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} else {
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0
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}
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}
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0x1e => self.queue_select, // notify_off
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_ => 0,
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}
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}
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fn write_common_config_word(&mut self, offset: u64, value: u16, queues: &mut [Queue]) {
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match offset {
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0x10 => self.msix_config = value,
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0x16 => self.queue_select = value,
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0x18 => self.with_queue_mut(queues, |q| q.size = value),
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0x1a => self.with_queue_mut(queues, |q| q.vector = value),
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0x1c => self.with_queue_mut(queues, |q| q.ready = value == 1),
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_ => {
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warn!("invalid virtio register word write: 0x{:x}", offset);
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}
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}
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}
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fn read_common_config_dword(&self, offset: u64, device: &dyn VirtioDevice) -> u32 {
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match offset {
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0x00 => self.device_feature_select,
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0x04 => {
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// Only 64 bits of features (2 pages) are defined for now, so limit
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// device_feature_select to avoid shifting by 64 or more bits.
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if self.device_feature_select < 2 {
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(device.features() >> (self.device_feature_select * 32)) as u32
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} else {
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0
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}
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}
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0x08 => self.driver_feature_select,
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_ => 0,
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}
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}
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fn write_common_config_dword(
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&mut self,
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offset: u64,
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value: u32,
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queues: &mut [Queue],
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device: &mut dyn VirtioDevice,
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) {
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fn hi(v: &mut GuestAddress, x: u32) {
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*v = (*v & 0xffffffff) | ((x as u64) << 32)
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}
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fn lo(v: &mut GuestAddress, x: u32) {
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*v = (*v & !0xffffffff) | (x as u64)
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}
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match offset {
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0x00 => self.device_feature_select = value,
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0x08 => self.driver_feature_select = value,
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0x0c => {
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if self.driver_feature_select < 2 {
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let features: u64 = (value as u64) << (self.driver_feature_select * 32);
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device.ack_features(features);
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for queue in queues.iter_mut() {
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queue.ack_features(features);
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}
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} else {
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warn!(
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"invalid ack_features (page {}, value 0x{:x})",
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self.driver_feature_select, value
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);
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}
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}
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0x20 => self.with_queue_mut(queues, |q| lo(&mut q.desc_table, value)),
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0x24 => self.with_queue_mut(queues, |q| hi(&mut q.desc_table, value)),
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0x28 => self.with_queue_mut(queues, |q| lo(&mut q.avail_ring, value)),
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0x2c => self.with_queue_mut(queues, |q| hi(&mut q.avail_ring, value)),
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0x30 => self.with_queue_mut(queues, |q| lo(&mut q.used_ring, value)),
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0x34 => self.with_queue_mut(queues, |q| hi(&mut q.used_ring, value)),
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_ => {
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warn!("invalid virtio register dword write: 0x{:x}", offset);
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}
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}
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}
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fn read_common_config_qword(&self, _offset: u64) -> u64 {
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0 // Assume the guest has no reason to read write-only registers.
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}
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fn write_common_config_qword(&mut self, offset: u64, value: u64, queues: &mut [Queue]) {
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match offset {
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0x20 => self.with_queue_mut(queues, |q| q.desc_table = GuestAddress(value)),
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0x28 => self.with_queue_mut(queues, |q| q.avail_ring = GuestAddress(value)),
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0x30 => self.with_queue_mut(queues, |q| q.used_ring = GuestAddress(value)),
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_ => {
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warn!("invalid virtio register qword write: 0x{:x}", offset);
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}
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}
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}
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fn with_queue<U, F>(&self, queues: &[Queue], f: F) -> Option<U>
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where
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F: FnOnce(&Queue) -> U,
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{
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queues.get(self.queue_select as usize).map(f)
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}
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fn with_queue_mut<F: FnOnce(&mut Queue)>(&self, queues: &mut [Queue], f: F) {
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if let Some(queue) = queues.get_mut(self.queue_select as usize) {
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f(queue);
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}
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}
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}
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#[cfg(test)]
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mod tests {
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use super::*;
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use base::{Event, RawDescriptor};
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use vm_memory::GuestMemory;
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struct DummyDevice(u32);
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const QUEUE_SIZE: u16 = 256;
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const QUEUE_SIZES: &'static [u16] = &[QUEUE_SIZE];
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const DUMMY_FEATURES: u64 = 0x5555_aaaa;
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impl VirtioDevice for DummyDevice {
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fn keep_rds(&self) -> Vec<RawDescriptor> {
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Vec::new()
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}
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fn device_type(&self) -> u32 {
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return self.0;
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}
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fn queue_max_sizes(&self) -> &[u16] {
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QUEUE_SIZES
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}
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fn activate(
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&mut self,
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_mem: GuestMemory,
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_interrupt: Interrupt,
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_queues: Vec<Queue>,
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_queue_evts: Vec<Event>,
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) {
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}
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fn features(&self) -> u64 {
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DUMMY_FEATURES
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}
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}
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#[test]
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fn write_base_regs() {
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let mut regs = VirtioPciCommonConfig {
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driver_status: 0xaa,
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config_generation: 0x55,
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device_feature_select: 0x0,
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driver_feature_select: 0x0,
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queue_select: 0xff,
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msix_config: 0x00,
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};
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let dev = &mut DummyDevice(0) as &mut dyn VirtioDevice;
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let mut queues = Vec::new();
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// Can set all bits of driver_status.
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regs.write(0x14, &[0x55], &mut queues, dev);
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let mut read_back = vec![0x00];
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regs.read(0x14, &mut read_back, &mut queues, dev);
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assert_eq!(read_back[0], 0x55);
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// The config generation register is read only.
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regs.write(0x15, &[0xaa], &mut queues, dev);
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let mut read_back = vec![0x00];
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regs.read(0x15, &mut read_back, &mut queues, dev);
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assert_eq!(read_back[0], 0x55);
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// Device features is read-only and passed through from the device.
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regs.write(0x04, &[0, 0, 0, 0], &mut queues, dev);
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let mut read_back = [0u8; 4];
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regs.read(0x04, &mut read_back, &mut queues, dev);
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assert_eq!(u32::from_le_bytes(read_back), DUMMY_FEATURES as u32);
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// Feature select registers are read/write.
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regs.write(0x00, &[1, 2, 3, 4], &mut queues, dev);
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let mut read_back = [0u8; 4];
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regs.read(0x00, &mut read_back, &mut queues, dev);
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assert_eq!(u32::from_le_bytes(read_back), 0x0403_0201);
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regs.write(0x08, &[1, 2, 3, 4], &mut queues, dev);
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let mut read_back = [0u8; 4];
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regs.read(0x08, &mut read_back, &mut queues, dev);
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assert_eq!(u32::from_le_bytes(read_back), 0x0403_0201);
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// 'queue_select' can be read and written.
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regs.write(0x16, &[0xaa, 0x55], &mut queues, dev);
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let mut read_back = vec![0x00, 0x00];
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regs.read(0x16, &mut read_back, &mut queues, dev);
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assert_eq!(read_back[0], 0xaa);
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assert_eq!(read_back[1], 0x55);
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}
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}
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