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https://chromium.googlesource.com/crosvm/crosvm
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7434c00020
The PIT implementation has the assumption that addresses are I/O port numbers, so we should use full address mode. i8042 is also changed to full address mode to avoid the conflict on port 0x61. BUG=chromium:908689 TEST=None Change-Id: Ibbb851e3a46ac7fc71576990a1618196de92e33c Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/1945794 Commit-Queue: Zhuocheng Ding <zhuocheng.ding@intel.corp-partner.google.com> Reviewed-by: Daniel Verkamp <dverkamp@chromium.org> Reviewed-by: Stephen Barber <smbarber@chromium.org> Tested-by: kokoro <noreply+kokoro@google.com>
45 lines
1.4 KiB
Rust
45 lines
1.4 KiB
Rust
// Copyright 2017 The Chromium OS Authors. All rights reserved.
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// Use of this source code is governed by a BSD-style license that can be
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// found in the LICENSE file.
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use sys_util::{error, EventFd};
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use crate::BusDevice;
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/// A i8042 PS/2 controller that emulates just enough to shutdown the machine.
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pub struct I8042Device {
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reset_evt: EventFd,
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}
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impl I8042Device {
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/// Constructs a i8042 device that will signal the given event when the guest requests it.
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pub fn new(reset_evt: EventFd) -> I8042Device {
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I8042Device { reset_evt }
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}
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}
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// i8042 device is mapped I/O address 0x61. We partially implement two 8-bit
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// registers: port 0x61 (I8042_PORT_B_REG), and port 0x64 (I8042_COMMAND_REG).
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impl BusDevice for I8042Device {
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fn debug_label(&self) -> String {
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"i8042".to_owned()
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}
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fn read(&mut self, offset: u64, data: &mut [u8]) {
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if data.len() == 1 && offset == 0x64 {
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data[0] = 0x0;
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} else if data.len() == 1 && offset == 0x61 {
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// Like kvmtool, we return bit 5 set in I8042_PORT_B_REG to
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// avoid hang in pit_calibrate_tsc() in Linux kernel.
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data[0] = 0x20;
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}
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}
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fn write(&mut self, offset: u64, data: &[u8]) {
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if data.len() == 1 && data[0] == 0xfe && offset == 0x64 {
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if let Err(e) = self.reset_evt.write(1) {
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error!("failed to trigger i8042 reset event: {}", e);
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}
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}
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}
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}
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