Xiong Zhang e93b16cefc x86_64: Redesign MTRR setting ... Currently MTRR setting is: the default cache type is write back and the pci low mmio range is uncache, then guest memory is WB by default, but pci high mmio and the gap between ram end and pci start below 4G are WB also, this part is wrong. In order to fix it, var mtrr should be used to set pci high mmio as uncache, but pci high mmio is too large to have enough var mtrrs. This commit change MTRR setting as: the default cache type is uncache, and the guest memory is WB. So memory range below 4G and above 4G are passed into setup_msrs(). And the variable MTRR registers are limited and have base and length requirement, so guest memory size is aligned to 256MB to avoid MTRR failure. BUG=None TEST=check guest mtrr setting with different guest memory size Change-Id: I4c18e83ce5e7fac9ac1bf6e174116a69924184ac Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3578015 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Junichi Uekawa <uekawa@chromium.org> Commit-Queue: Junichi Uekawa <uekawa@chromium.org>		2022-04-25 06:11:45 +00:00
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src	x86_64: Redesign MTRR setting	2022-04-25 06:11:45 +00:00
Cargo.toml	Update to gdbstub 0.6.1	2022-04-13 12:52:24 +00:00