mirror of
https://chromium.googlesource.com/crosvm/crosvm
synced 2025-02-11 04:26:38 +00:00
1dab58a2cf
This search/replace updates all copyright notices to drop the "All rights reserved", Use "ChromiumOS" instead of "Chromium OS" and drops the trailing dots. This fulfills the request from legal and unifies our notices. ./tools/health-check has been updated to only accept this style. BUG=b:246579983 TEST=./tools/health-check Change-Id: I87a80701dc651f1baf4820e5cc42469d7c5f5bf7 Reviewed-on: https://chromium-review.googlesource.com/c/crosvm/crosvm/+/3894243 Reviewed-by: Daniel Verkamp <dverkamp@chromium.org> Commit-Queue: Dennis Kempin <denniskempin@google.com>
366 lines
11 KiB
Rust
366 lines
11 KiB
Rust
// Copyright 2020 The ChromiumOS Authors
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// Use of this source code is governed by a BSD-style license that can be
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// found in the LICENSE file.
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use std::arch::x86_64::CpuidResult;
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use std::arch::x86_64::__cpuid;
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use std::sync::atomic::AtomicBool;
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use std::sync::atomic::Ordering;
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use base::AsRawDescriptor;
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use base::RawDescriptor;
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use base::Result;
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use base::SafeDescriptor;
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use crate::CpuId;
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use crate::CpuIdEntry;
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use crate::Hypervisor;
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use crate::HypervisorCap;
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use crate::HypervisorX86_64;
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mod haxm_sys;
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// This is a HAXM-specific capability, so it's not present in the VmCap enum, and the
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// register_vm_log function does not exist on the Vm trait. But windows.rs will use it when
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// creating Haxm Vm instances, so we expose the cap constant here.
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pub use haxm_sys::HAX_CAP_VM_LOG;
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use haxm_sys::*;
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mod vcpu;
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pub use vcpu::*;
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mod vm;
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pub use vm::*;
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#[cfg(windows)]
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mod win;
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#[cfg(windows)]
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use win::*;
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#[cfg(unix)]
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mod unix;
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#[cfg(unix)]
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use unix::*;
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static USE_GHAXM: AtomicBool = AtomicBool::new(true);
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/// Returns whether ghaxm variant is in use vs. the upstream haxm variant.
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pub fn get_use_ghaxm() -> bool {
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USE_GHAXM.load(Ordering::Relaxed)
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}
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/// Sets whether to use ghaxm variant vs. the upstream haxm variant.
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pub fn set_use_ghaxm(use_ghaxm: bool) {
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USE_GHAXM.store(use_ghaxm, Ordering::Relaxed);
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}
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pub struct Haxm {
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haxm: SafeDescriptor,
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}
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impl AsRawDescriptor for Haxm {
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fn as_raw_descriptor(&self) -> RawDescriptor {
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self.haxm.as_raw_descriptor()
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}
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}
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impl Haxm {
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/// Opens HAXM device and returns a Haxm object on success.
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pub fn new() -> Result<Haxm> {
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Ok(Haxm {
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haxm: open_haxm_device(get_use_ghaxm())?,
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})
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}
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}
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impl Hypervisor for Haxm {
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fn check_capability(&self, cap: HypervisorCap) -> bool {
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// under haxm, guests rely on this leaf to calibrate their
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// clocksource.
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matches!(
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cap,
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HypervisorCap::UserMemory | HypervisorCap::CalibratedTscLeafRequired
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)
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}
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/// Makes a shallow clone of this `Hypervisor`.
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fn try_clone(&self) -> Result<Self> {
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Ok(Haxm {
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haxm: self.haxm.try_clone()?,
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})
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}
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}
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impl HypervisorX86_64 for Haxm {
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fn get_supported_cpuid(&self) -> Result<CpuId> {
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// Start with cpuids that HAXM supports from
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// https://github.com/intel/haxm/blob/v7.6.1/core/cpuid.c#L170
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let mut supported_features_1_ecx = (Feature1Ecx::SSE3
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| Feature1Ecx::SSSE3
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| Feature1Ecx::PCID
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| Feature1Ecx::SSE41
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| Feature1Ecx::SSE42
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| Feature1Ecx::CMPXCHG16B
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| Feature1Ecx::MOVBE
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| Feature1Ecx::AESNI
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| Feature1Ecx::PCLMULQDQ
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| Feature1Ecx::POPCNT
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| Feature1Ecx::FMA
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| Feature1Ecx::XSAVE
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| Feature1Ecx::OSXSAVE
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| Feature1Ecx::AVX
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| Feature1Ecx::F16C
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| Feature1Ecx::RDRAND)
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.bits();
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let mut supported_features_1_edx = (Feature1Edx::PAT
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| Feature1Edx::FPU
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| Feature1Edx::VME
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| Feature1Edx::DE
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| Feature1Edx::TSC
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| Feature1Edx::MSR
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| Feature1Edx::PAE
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| Feature1Edx::MCE
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| Feature1Edx::CX8
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| Feature1Edx::APIC
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| Feature1Edx::SEP
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| Feature1Edx::MTRR
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| Feature1Edx::PGE
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| Feature1Edx::MCA
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| Feature1Edx::CMOV
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| Feature1Edx::CLFSH
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| Feature1Edx::MMX
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| Feature1Edx::FXSR
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| Feature1Edx::SSE
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| Feature1Edx::SSE2
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| Feature1Edx::SS
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| Feature1Edx::PSE
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| Feature1Edx::HTT)
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.bits();
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let mut supported_features_80000001_edx = (Feature80000001Edx::NX
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| Feature80000001Edx::SYSCALL
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| Feature80000001Edx::RDTSCP
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| Feature80000001Edx::EM64T)
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.bits();
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let mut supported_features_80000001_ecx =
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(Feature80000001Ecx::LAHF | Feature80000001Ecx::ABM | Feature80000001Ecx::PREFETCHW)
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.bits();
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let result = unsafe { __cpuid(0x1) };
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// Filter HAXM supported cpuids by host-supported cpuids
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supported_features_1_ecx &= result.ecx;
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supported_features_1_edx &= result.edx;
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let result = unsafe { __cpuid(0x80000001) };
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supported_features_80000001_edx &= result.edx;
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supported_features_80000001_ecx &= result.ecx;
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let cpuid_7 = unsafe { __cpuid(0x7) };
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let cpuid_15 = unsafe { __cpuid(0x15) };
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let cpuid_16 = unsafe { __cpuid(0x16) };
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Ok(CpuId {
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cpu_id_entries: vec![
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CpuIdEntry {
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function: 0x1,
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index: 0,
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flags: 0,
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cpuid: CpuidResult {
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eax: 0,
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ebx: 0,
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ecx: supported_features_1_ecx,
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edx: supported_features_1_edx,
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},
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},
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CpuIdEntry {
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function: 0x7,
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index: 0,
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flags: 0,
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cpuid: CpuidResult {
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eax: cpuid_7.eax,
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ebx: cpuid_7.ebx,
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ecx: cpuid_7.ecx,
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edx: cpuid_7.edx,
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},
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},
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CpuIdEntry {
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function: 0x15,
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index: 0,
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flags: 0,
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cpuid: CpuidResult {
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eax: cpuid_15.eax,
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ebx: cpuid_15.ebx,
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ecx: cpuid_15.ecx,
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edx: cpuid_15.edx,
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},
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},
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CpuIdEntry {
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function: 0x16,
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index: 0,
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flags: 0,
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cpuid: CpuidResult {
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eax: cpuid_16.eax,
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ebx: cpuid_16.ebx,
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ecx: cpuid_16.ecx,
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edx: cpuid_16.edx,
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},
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},
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CpuIdEntry {
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function: 0x80000001,
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index: 0,
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flags: 0,
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cpuid: CpuidResult {
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eax: 0,
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ebx: 0,
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ecx: supported_features_80000001_ecx,
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edx: supported_features_80000001_edx,
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},
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},
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],
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})
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}
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fn get_emulated_cpuid(&self) -> Result<CpuId> {
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// HAXM does not emulate any cpuids that the host does not support
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Ok(CpuId::new(0))
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}
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/// Gets the list of supported MSRs.
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fn get_msr_index_list(&self) -> Result<Vec<u32>> {
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// HAXM supported MSRs come from
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// https://github.com/intel/haxm/blob/v7.6.1/core/vcpu.c#L3296
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let mut msrs = vec![
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IA32_TSC,
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IA32_FEATURE_CONTROL,
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IA32_PLATFORM_ID,
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IA32_APIC_BASE,
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IA32_EFER,
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IA32_STAR,
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IA32_LSTAR,
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IA32_CSTAR,
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IA32_SF_MASK,
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IA32_KERNEL_GS_BASE,
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IA32_TSC_AUX,
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IA32_FS_BASE,
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IA32_GS_BASE,
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IA32_SYSENTER_CS,
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IA32_SYSENTER_ESP,
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IA32_SYSENTER_EIP,
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IA32_MTRRCAP,
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MTRRFIX64K_00000,
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IA32_CR_PAT,
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IA32_MTRR_DEF_TYPE,
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IA32_MCG_CAP,
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IA32_MCG_STATUS,
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IA32_MCG_CTL,
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IA32_MC0_CTL,
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IA32_P5_MC_TYPE,
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IA32_MC0_STATUS,
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IA32_P5_MC_ADDR,
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IA32_MC0_ADDR,
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IA32_MC0_MISC,
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IA32_THERM_DIODE_OFFSET,
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IA32_FSB_FREQ,
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IA32_TEMP_TARGET,
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IA32_BBL_CR_CTL3,
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IA32_DEBUGCTL,
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IA32_CPUID_FEATURE_MASK,
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IA32_EBC_FREQUENCY_ID,
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IA32_EBC_HARD_POWERON,
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IA32_EBC_SOFT_POWERON,
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IA32_BIOS_SIGN_ID,
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IA32_MISC_ENABLE,
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IA32_PERF_CAPABILITIES,
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IA32_PMC0,
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IA32_PMC1,
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IA32_PMC2,
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IA32_PMC3,
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IA32_PERFEVTSEL0,
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IA32_PERFEVTSEL1,
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IA32_PERFEVTSEL2,
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IA32_PERFEVTSEL3,
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];
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msrs.extend(IA32_MTRR_PHYSBASE0..IA32_MTRR_PHYSMASK9);
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msrs.extend(MTRRFIX16K_80000..MTRRFIX16K_A0000);
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msrs.extend(MTRRFIX4K_C0000..MTRRFIX4K_F8000);
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msrs.extend(IA32_MC0_CTL2..IA32_MC8_CTL2);
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Ok(msrs)
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}
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}
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// TODO(b:241252288): Enable tests disabled with dummy feature flag - enable_haxm_tests.
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#[cfg(test)]
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#[cfg(feature = "enable_haxm_tests")]
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mod tests {
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use super::*;
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#[test]
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fn new_haxm() {
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Haxm::new().expect("failed to instantiate HAXM");
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}
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#[test]
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fn check_capability() {
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let haxm = Haxm::new().expect("failed to instantiate HAXM");
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assert!(haxm.check_capability(HypervisorCap::UserMemory));
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assert!(!haxm.check_capability(HypervisorCap::ImmediateExit));
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}
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#[test]
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fn check_supported_cpuid() {
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let haxm = Haxm::new().expect("failed to instantiate HAXM");
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let cpuid = haxm
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.get_supported_cpuid()
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.expect("failed to get supported cupid");
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// HAXM returns five leaves: 0x1, 0x7, 0x15, 0x16, and 0x80000001
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assert_eq!(cpuid.cpu_id_entries.len(), 5);
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// Check some simple cpuids that we know should be enabled
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let entry = cpuid
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.cpu_id_entries
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.iter()
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.find(|entry| entry.function == 0x1)
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.expect("failed to get leaf 0x1");
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// FPU should definitely exist
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assert_ne!(entry.cpuid.edx & Feature1Edx::FPU.bits(), 0);
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// SSSE3 almost certainly set
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assert_ne!(entry.cpuid.ecx & Feature1Ecx::SSSE3.bits(), 0);
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// VMX should not be set, HAXM does not support nested virt
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assert_eq!(entry.cpuid.ecx & Feature1Ecx::VMX.bits(), 0);
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// Check that leaf 0x15 is in the results
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cpuid
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.cpu_id_entries
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.iter()
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.find(|entry| entry.function == 0x15)
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.expect("failed to get leaf 0x15");
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// Check that leaf 0x16 is in the results
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cpuid
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.cpu_id_entries
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.iter()
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.find(|entry| entry.function == 0x16)
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.expect("failed to get leaf 0x16");
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let entry = cpuid
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.cpu_id_entries
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.iter()
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.find(|entry| entry.function == 0x80000001)
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.expect("failed to get leaf 0x80000001");
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// NX should be set, Windows 8+ and HAXM require it
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assert_ne!(entry.cpuid.edx & Feature80000001Edx::NX.bits(), 0);
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}
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#[test]
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fn check_msr_index_list() {
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let haxm = Haxm::new().expect("failed to instantiate HAXM");
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let msr_index_list = haxm
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.get_msr_index_list()
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.expect("failed to get HAXM msr index list");
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assert!(msr_index_list.contains(&IA32_TSC));
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}
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}
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