Zixuan Chen 82b5f8dc90 Perf: speed up utf16 and wasm (#90) ... * perf: remove unused transact field * perf: micro optimization * bench: fix bench * bench: add utf16 bench * chore: refine diagnose * perf: speedup utf16 lookup * perf: use better utf16 len counter * refactor: use js to cast Loro/Transaction * refactor: map and list use __loro and __txn * test: configure ci vitest * chore: ci		2023-04-03 09:29:25 +08:00
..
rle_tree	fix: encode use dep_on_self	2023-02-22 14:10:21 +08:00
lib.rs	fix: vec slice is ill defined	2022-12-06 15:50:35 +08:00
range_map.excalidraw	doc: update range map doc	2022-11-10 12:00:05 +08:00
range_map.rs	fix: make LoroCore: Send + Sync (#61)	2023-01-06 21:03:11 +08:00
rle_impl.rs	Perf remove string pool mutex (#41)	2022-12-13 16:18:56 +08:00
rle_trait.rs	feat: add delta compose	2023-03-01 14:12:05 +08:00
rle_tree.rs	Perf: speed up utf16 and wasm (#90)	2023-04-03 09:29:25 +08:00
rle_vec.rs	fix: vec slice is ill defined	2022-12-06 15:50:35 +08:00
rle_vec_old.rs	feat: add delta compose	2023-03-01 14:12:05 +08:00
small_set.rs
test.rs	refactor: remove proptest feature	2022-11-13 21:22:49 +08:00