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make aarch64 pci dma-coherent

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On arm, if the device is not coherent, guest kernel will allocate dma memory as
no-cacheable. Crosvm on the host user space thinks the memory is
cacheable. Thus when guest kernel write to dma memory, it will bypass
the cache, crosvm won't see the change.

BUG=None
TEST=local build and test

Change-Id: If6cf2d28afec61d5beb136628116ff9e7e0483f4
Reviewed-on: https://chromium-review.googlesource.com/1497739
Commit-Ready: Jingkui Wang <jkwang@google.com>
Tested-by: Jingkui Wang <jkwang@google.com>
Reviewed-by: Sonny Rao <sonnyrao@chromium.org>
Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
This commit is contained in:
Jingkui Wang 2019-03-02 02:37:54 -08:00 committed by chrome-bot
parent c69f97542a
commit 2de0088c9e
1 changed files with 1 additions and 0 deletions
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aarch64/src/fdt.rs
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@ -252,6 +252,7 @@ fn create_pci_nodes(
property_u32(fdt, "#interrupt-cells", 1)?;
property(fdt, "interrupt-map", &interrupt_map)?;
property(fdt, "interrupt-map-mask", &interrupt_map_mask)?;
property_null(fdt, "dma-coherent")?;
end_node(fdt)?;
Ok(())