mirror of
https://chromium.googlesource.com/crosvm/crosvm
synced 2025-02-11 04:26:38 +00:00
c96e46c6a9
Since all pcie ports (root port, upstream port, downstream port) have similiar pci config space and handling logic, we could have a common code base for them to use for code simplicity. This patch adds the code base PciePort structure that could be used later for both pcie root port and pcie upstream/downstream port. BUG=b:199986018 TEST=./tools/presubmit Change-Id: I23cfaf561432ed2cb977d0d2a020fc05370bb4b0 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3692429 Reviewed-by: Daniel Verkamp <dverkamp@chromium.org> Tested-by: kokoro <noreply+kokoro@google.com> Commit-Queue: Daniel Verkamp <dverkamp@chromium.org> |
||
|---|---|---|
| .. | ||
| irqchip | ||
| pci | ||
| platform | ||
| register_space | ||
| sys | ||
| tsc | ||
| usb | ||
| utils | ||
| virtio | ||
| acpi.rs | ||
| bat.rs | ||
| bus.rs | ||
| cmos.rs | ||
| debugcon.rs | ||
| direct_io.rs | ||
| direct_irq.rs | ||
| i8042.rs | ||
| irq_event.rs | ||
| lib.rs | ||
| pit.rs | ||
| pl030.rs | ||
| proxy.rs | ||
| serial.rs | ||
| serial_device.rs | ||
| software_tpm.rs | ||
| sys.rs | ||
| tsc.rs | ||
| vfio.rs | ||