mirror of
https://chromium.googlesource.com/crosvm/crosvm
synced 2025-02-11 12:35:26 +00:00
45a94bedae
The current vhost-net msix irq injection flow is from vhost-kernel to crosvm vhost-net, then to the KVM for irq injection. It still need crosvm vhost-net to trigger irq, which is because the set_vring_call is not directly using the msix irq fd. To optimize this flow to be from vhost-kernel to KVM directly, need: 1. if the msix is enabled and unmasked, use the misx irq fd for the vring_call directly so that all the misx injection can directly to KVM from vhost-kernel. 2. if the msix is disabled or masked, use the indirect vhost_interrupt fd to let the crosvm to control the irq injection. BUG=None TEST=cargo test -p devices TEST=start crosvm with vhost-net, and run the iperf3 on the network without any issue Change-Id: Idb3427f69f23b728305ed63d88973156a03e7c6b Signed-off-by: Chuanxiao Dong <chuanxiao.dong@intel.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/2046452 Reviewed-by: Stephen Barber <smbarber@chromium.org> Tested-by: kokoro <noreply+kokoro@google.com>
42 lines
1.1 KiB
Rust
42 lines
1.1 KiB
Rust
// Copyright 2018 The Chromium OS Authors. All rights reserved.
|
|
// Use of this source code is governed by a BSD-style license that can be
|
|
// found in the LICENSE file.
|
|
|
|
//! Implements pci devices and busses.
|
|
|
|
mod ac97;
|
|
mod ac97_bus_master;
|
|
mod ac97_mixer;
|
|
mod ac97_regs;
|
|
mod msix;
|
|
mod pci_configuration;
|
|
mod pci_device;
|
|
mod pci_root;
|
|
mod vfio_pci;
|
|
|
|
pub use self::ac97::{Ac97Backend, Ac97Dev, Ac97Parameters};
|
|
pub use self::msix::{MsixCap, MsixConfig, MsixStatus};
|
|
pub use self::pci_configuration::{
|
|
PciBarConfiguration, PciBarPrefetchable, PciBarRegionType, PciCapability, PciCapabilityID,
|
|
PciClassCode, PciConfiguration, PciHeaderType, PciProgrammingInterface, PciSerialBusSubClass,
|
|
PciSubclass,
|
|
};
|
|
pub use self::pci_device::Error as PciDeviceError;
|
|
pub use self::pci_device::PciDevice;
|
|
pub use self::pci_root::{PciConfigIo, PciConfigMmio, PciRoot};
|
|
pub use self::vfio_pci::VfioPciDevice;
|
|
|
|
/// PCI has four interrupt pins A->D.
|
|
#[derive(Copy, Clone)]
|
|
pub enum PciInterruptPin {
|
|
IntA,
|
|
IntB,
|
|
IntC,
|
|
IntD,
|
|
}
|
|
|
|
impl PciInterruptPin {
|
|
pub fn to_mask(self) -> u32 {
|
|
self as u32
|
|
}
|
|
}
|