Now that we're trying to change how we copy cpuid, let's add a way to
test them.
BUG=None
TEST=tools/dev_container cargo test -p x86_64 --features=direct
Change-Id: Ic5f1a59b6f0bcda809b908ba2e852e8b03e037a2
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3716013
Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: Junichi Uekawa <uekawa@chromium.org>
So that a copy becomes a straightforward copy.
We were copy-pasting eax ebx ecx edx many times here.
BUG=None
TEST=build
Change-Id: Ibdabdd0da3876159bda3d29aa2a3927b9a3f40ae
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3717927
Commit-Queue: Junichi Uekawa <uekawa@chromium.org>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
Reviewed-by: Keiichi Watanabe <keiichiw@chromium.org>
* Splits platform specific bits of test_integration into a sys module.
* Cleans up Cargo.toml & platform specific imports.
BUG=b:213152505
TEST=builds
Change-Id: I95eff1f240e98b09a600239a77fc54e5222edebf
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3701040
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
Reviewed-by: Richard Zhang <rizhang@google.com>
Commit-Queue: Noah Gold <nkgold@google.com>
The new LoadedKernel structure also splits out the size and end address,
which are both used in different places (x86_64 wants end, aarch64 wants
both).
BUG=b:234155022
TEST=tools/presubmit
TEST=cargo test -p kernel_loader
Change-Id: I86a7e412c983f29a2c614cc9e6896aa11db6ba94
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3673611
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: Daniel Verkamp <dverkamp@chromium.org>
Reviewed-by: Alexandre Courbot <acourbot@chromium.org>
This is a reland of commit 7110d673f2
Replace --no-legacy flag, which implied the removal of both i8042 and
rtc devices, with separate --no-i8042 and --no-rtc flags. The old
flag is still supported and implies the other two.
Because the original landing of this flag didn't protect it as an x86
specific option, this change just leaves that alone. But the new flags
are added as x86-only, because they are very x86 specific.
BUG=b:223443221
TEST=crosvm run --bios u-boot.rom --disk kernel
TEST=boot volteer-manatee
Change-Id: I57f9328483f24da29db663e261b3ccc2a97c3239
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3715083
Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
Reviewed-by: Keiichi Watanabe <keiichiw@chromium.org>
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: Daniel Verkamp <dverkamp@chromium.org>
This reverts commit 7110d673f2.
Reason for revert: Needs to preserve --no-legacy flag for a while though deprecated
Original change's description:
> crosvm: split up --no-legacy flag
>
> Replace --no-legacy flag, which implied the removal of both i8042 and
> rtc devices, with separate --no-i8042 and --no-rtc flags. The old
> flag is still supported and implies the other two.
>
> Because the original landing of this flag didn't protect it as an x86
> specific option, this change just leaves that alone. But the new flags
> are added as x86-only, because they are very x86 specific.
>
> BUG=b:223443221
> TEST=crosvm run --bios u-boot.rom --disk kernel
>
> Change-Id: I4bbea2d0a38fdd3a5d69d12ca79fa360f0460358
> Signed-off-by: Alistair Delva <adelva@google.com>
> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3510982
> Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
> Commit-Queue: Daniel Verkamp <dverkamp@chromium.org>
> Tested-by: kokoro <noreply+kokoro@google.com>
Bug: b:223443221
Change-Id: I022cff96f4508713c15973ee37a57e7fdc8c14e3
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3715073
Bot-Commit: Rubber Stamper <rubber-stamper@appspot.gserviceaccount.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: Junichi Uekawa <uekawa@chromium.org>
Reviewed-by: Keiichi Watanabe <keiichiw@chromium.org>
This will be used to pass the initial register values for each vcpu.
Each architecture can define its own variant of the initial vcpu state.
BUG=b:234155022
TEST=tools/presubmit --all
Change-Id: I696a5ecda202c1ff0681f0b89b89b9eec11e27e7
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3673615
Reviewed-by: Anton Romanov <romanton@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: Daniel Verkamp <dverkamp@chromium.org>
This allows irq processing thread to log statistics and metrics and
track them using the source of the device. To be upstreamed later.
Introduce `PCI_VENDOR_ID_CROSVM` which identifies devices created by
crosvm. And introduce `CrosvmDeviceId` which adds a unique device ID for
each type of crosvm device.
BUG=b:213149158
BUG=b:213152505
TEST=Compiled.
Change-Id: Ica1374d8a2d8fd627c9397553bb7fb62baeaff7d
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3687418
Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: Vaibhav Nagarnaik <vnagarnaik@google.com>
Exclude pci mmio region below 4gb from the e820 table. This is a
followup to CL:3696671.
BUG=None
TEST=arc.Boot.vm
Change-Id: I07c2b9a9e2e4e27682c4b60406625b019eea195f
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3708390
Reviewed-by: Junichi Uekawa <uekawa@chromium.org>
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: David Stevens <stevensd@chromium.org>
Make `cargo test --feauture=direct` pass by fixing build dependencies
and skipping a broken test case.
BUG=b:220292205
TEST=cargo build --features=direct in x86_64
Change-Id: I599ad5bc7ebb2fa91f6ff64291fb15ea129f8d05
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3708381
Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: Keiichi Watanabe <keiichiw@chromium.org>
The AddressRange type is used for representing contiguous memory or I/O
address ranges, mostly equivalent to RangeInclusive<u64> but with the
added benefit of implementing Copy and not carrying an extra field used
only for iteration, which we don't need.
Using an inclusive range means we can represent the full address space
with no weird corner cases around the upper limit of the range (for
example, an AddressRange covering the full 64-bit space can be
represented as start: 0, end: u64::MAX).
AddressRange also replaces the previous MemRegion type, which was a
start/size pair.
This normalizes the interface of the resources crates to use
AddressRange rather than a start/size pair; more cleanups throughout the
tree may be possible, but this commit attempts to be somewhat smaller to
have a hope of being reviewable.
BUG=b:222769529
TEST=tools/presubmit --all
TEST=cargo test -p resources
Change-Id: I8c90bdc28456221b5107ef7e589233315ea739c3
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3696671
Reviewed-by: Junichi Uekawa <uekawa@chromium.org>
Reviewed-by: David Stevens <stevensd@chromium.org>
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: Daniel Verkamp <dverkamp@chromium.org>
Replace --no-legacy flag, which implied the removal of both i8042 and
rtc devices, with separate --no-i8042 and --no-rtc flags. The old
flag is still supported and implies the other two.
Because the original landing of this flag didn't protect it as an x86
specific option, this change just leaves that alone. But the new flags
are added as x86-only, because they are very x86 specific.
BUG=b:223443221
TEST=crosvm run --bios u-boot.rom --disk kernel
Change-Id: I4bbea2d0a38fdd3a5d69d12ca79fa360f0460358
Signed-off-by: Alistair Delva <adelva@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3510982
Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
Commit-Queue: Daniel Verkamp <dverkamp@chromium.org>
Tested-by: kokoro <noreply+kokoro@google.com>
Add Goldfish battery to aarch64 crosvm. The guest kernel will
see the goldfish battery node on the FDT.
This copies the seccomp policy for the battery from x86-64.
BUG=b:214124318
TEST=create VM with parameter "--battery" or "--battery=type=goldfish"
TEST=android-sh -c 'dumpsys battery'
TEST=tast run ${DUT} arc.PerfBoot.vm
Change-Id: I8212e760db5ffbc5d01442cfa7930baa5962ef6e
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3686713
Reviewed-by: Alexandre Courbot <acourbot@chromium.org>
Tested-by: kokoro <noreply+kokoro@google.com>
Auto-Submit: Masami Hiramatsu <mhiramat@google.com>
Reviewed-by: Keiichi Watanabe <keiichiw@chromium.org>
Commit-Queue: Masami Hiramatsu <mhiramat@google.com>
Reworks the way we organize parameters to this module, and
adds CPU manufacturer detection.
BUG=213152505
TEST=builds
Change-Id: Ibb96f08cacbdfdaff5ef971c3d6d7b901b5d73fa
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3690369
Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
Commit-Queue: Noah Gold <nkgold@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Our BIOS doesn't set the TSC MSR to 0 on boot, but our hypervisors need
this to be set so they can correctly sync their TSC offsets. This
introduces a generic "reset_msrs" function where we currently reset the
TSC msr, but where we could also reset if we need to in the future.
Cherrypick from downstream branch.
Actual author: Colin Downs-Razouk <colindr@google.com>.
BUG=191981229
TEST=tested downstream
Change-Id: I17b5709411394ae48fb5d7310636636295ebfaad
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3690370
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
Commit-Queue: Noah Gold <nkgold@google.com>
Name the enums instead of bool so that it's easier to reason, and factor
out the MSR loop.
BUG=b:229770963
TEST=build
Change-Id: I7d2306472bdf7482479b40b0ef00f378754a811f
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3685671
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
Commit-Queue: Junichi Uekawa <uekawa@chromium.org>
Turbostat detects if CPU frequency and temperature features are
supported by reading several CPUID entries bits. Expose these
CPUID bits to guest when enable-pnp-data option is enabled.
Several MSR registers which turbostat depends on have been already
passed through when ITMT is enabled. Adding code to detect this and
avoid to doubly pass through.
BUG=b:229770963
TEST=Run "turbostat" in Chrome OS guest and show correct value.
Change-Id: Ieebaf616d544cb187a80ec6f3313a246ebf54bb2
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3641466
Reviewed-by: Junichi Uekawa <uekawa@chromium.org>
Commit-Queue: Junichi Uekawa <uekawa@chromium.org>
Tested-by: kokoro <noreply+kokoro@google.com>
turbostat shows cpu freq/c-state/thermal statistics data by reading
some related MSRs. Unfortunately some MSRs such as MSR_IA32_POWER_CTL
are already emulated by KVM. The emulated value are not what we want
to expose to Chrome OS guest. KVM_X86_SET_MSR_FILTER ioctl provides
a way to skip KVM's emulation and let user space handle the MSR.
We added two MSR actions "MsrPassthroughFilter" and "MsrEmulateFilter"
to indicate the corresponding MSR needs to be filtered.
BUG=b:229770963
TEST=Run "turbostat" in Chrome OS guest and show correct value.
Change-Id: I5920ddba091589170dc326e10187aec66f75df79
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3641465
Reviewed-by: Junichi Uekawa <uekawa@chromium.org>
Commit-Queue: Junichi Uekawa <uekawa@chromium.org>
Tested-by: kokoro <noreply+kokoro@google.com>
This is a reland of commit 129840471d
Original change's description:
> devices: debugcon: add bochs-style debugcon device
>
> This allows for creating a simple write-only debug connection that uses
> a single IO port. This method is supported by both bochs and qemu[1].
>
> The main motivation here is to help in improving crosvm's ability to
> boot OVMF, which makes use of this simple debug device on port 0x402.
> For that one would use `--serial
> type=stdout,hardware=debugcon,debugcon_port=1026` or something similar.
>
> Note that serde_keyvalue doesn't support parsing hex values, hence the
> need to use `1026`, but I intend to address that as well to allow the
> more natural `debugcon_port=0x402` phrasing.
>
> [1]: https://github.com/qemu/qemu/blob/master/hw/char/debugcon.c
>
> BUG=b:233610263
>
> Change-Id: I73238e5c35925668d133bfaa542fcbcf1e28765f
> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3661255
> Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
> Commit-Queue: Mike Gerow <gerow@google.com>
> Tested-by: kokoro <noreply+kokoro@google.com>
Bug: b:233610263
Change-Id: I2f2125da95e8907f4f0c16930952e9b765d33e6c
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3671087
Tested-by: kokoro <noreply+kokoro@google.com>
Auto-Submit: Mike Gerow <gerow@google.com>
Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
Commit-Queue: Daniel Verkamp <dverkamp@chromium.org>
This reverts commit 129840471d.
Reason for revert: This conflicts with https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3600167 breaking the build
Original change's description:
> devices: debugcon: add bochs-style debugcon device
>
> This allows for creating a simple write-only debug connection that uses
> a single IO port. This method is supported by both bochs and qemu[1].
>
> The main motivation here is to help in improving crosvm's ability to
> boot OVMF, which makes use of this simple debug device on port 0x402.
> For that one would use `--serial
> type=stdout,hardware=debugcon,debugcon_port=1026` or something similar.
>
> Note that serde_keyvalue doesn't support parsing hex values, hence the
> need to use `1026`, but I intend to address that as well to allow the
> more natural `debugcon_port=0x402` phrasing.
>
> [1]: https://github.com/qemu/qemu/blob/master/hw/char/debugcon.c
>
> BUG=b:233610263
>
> Change-Id: I73238e5c35925668d133bfaa542fcbcf1e28765f
> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3661255
> Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
> Commit-Queue: Mike Gerow <gerow@google.com>
> Tested-by: kokoro <noreply+kokoro@google.com>
Bug: b:233610263
Change-Id: Ia70540c3041611f59968cb7929b238eecfe2530d
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3671082
Bot-Commit: Rubber Stamper <rubber-stamper@appspot.gserviceaccount.com>
Auto-Submit: Mike Gerow <gerow@google.com>
Commit-Queue: Dennis Kempin <denniskempin@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Dennis Kempin <denniskempin@google.com>
This allows for creating a simple write-only debug connection that uses
a single IO port. This method is supported by both bochs and qemu[1].
The main motivation here is to help in improving crosvm's ability to
boot OVMF, which makes use of this simple debug device on port 0x402.
For that one would use `--serial
type=stdout,hardware=debugcon,debugcon_port=1026` or something similar.
Note that serde_keyvalue doesn't support parsing hex values, hence the
need to use `1026`, but I intend to address that as well to allow the
more natural `debugcon_port=0x402` phrasing.
[1]: https://github.com/qemu/qemu/blob/master/hw/char/debugcon.c
BUG=b:233610263
Change-Id: I73238e5c35925668d133bfaa542fcbcf1e28765f
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3661255
Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
Commit-Queue: Mike Gerow <gerow@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
BIOS expect all the cpus to be pointed at the i386 reset vector before
boot. We can't guarantee that a fresh vcpu will be pointed to the reset
vector by default, so we should set the reset vector when we're
configuring the vcpu when we're using a BIOS.
Cherrypick from downstream branch.
Actual author: Colin Downs-Razouk <colindr@google.com>.
TEST=builds
BUG=b:213152505
Change-Id: Idf4e0a200c8141adf5cbb83856cbd57362d84716
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3657811
Reviewed-by: Colin Downs-Razouk <colindr@google.com>
Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
Commit-Queue: Noah Gold <nkgold@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
crosvm waits on events like exit, reset, crash, guest panic etc and
uses eventfd to wait on these events. As of now, we have 4 eventfds
and may increase.
This is an attempt to consolidate all Vm events into one framework.
Use Tube instead of Event to get consistent behavior between OSes.
Implement a wrapper over Tube to have a consistent API for events.
BUG=None.
TEST=Built crosvm. Ran a minimal vm to panic and verified that crosvm
received the panic event. cargo test on devices.
Change-Id: I313d428de5e3ce3b879982f913918ec0a4a72c35
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3480577
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
Commit-Queue: Vineeth Pillai <vineethrp@google.com>
Reviewed-by: Noah Gold <nkgold@google.com>
Instead of calling method each time, prepare a list and then iterate
over so that it's clearer we are doing the same thing many times.
BUG=b:215297064
TEST=build
Change-Id: I2556a9c12baa90ac0e5fa98e488e0586b1a4f010
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3653341
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
Commit-Queue: Junichi Uekawa <uekawa@chromium.org>
To simplify the construction and parsing, and put the impossible values
checking at parameter parsing time.
BUG=b:215297064
TEST=build
Change-Id: Ic601d61a73dba9e3ec40f3589c62a586e1c7a8c3
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3655032
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
Commit-Queue: Junichi Uekawa <uekawa@chromium.org>
Some hypervisors (e.g. whpx) require that VM need to initialize their
`CPUID` early i.e. during VM creation. In this case, there is no
per-vcpu initialization of `CPUID`.
Allow this quirk through another entry in `VmCap` that avoids `CPUID`
initialization at vCPU creation time.
BUG=b:213150327
TEST=Compiled.
Change-Id: Ia74434ead1fff244042d03347c82cb73f243bdbb
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3654206
Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: Vaibhav Nagarnaik <vnagarnaik@google.com>
In order to let host and guest have ths similiar pci mmio layout in
manatee, this commit add a pci-start parameter.
BUG=b:197877871
TEST=boot vm with --pci-start and check vm's mmio layout
Change-Id: I0e83dfb3ab3c3b2ea1b0a1554d532e8414924b36
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3578017
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: Junichi Uekawa <uekawa@chromium.org>
Reviewed-by: Junichi Uekawa <uekawa@chromium.org>
Remove a few ioports that did nothing, but were specifically wired up to
stubs so they would not generate debug prints.
Port 0xed will only be used by Linux if io_delay=alternate is set on the
cmdline, which was only required for some quirky PC hardware.
Ports 0xf0 ("busy latch reset") and 0xf1 ("coprocessor reset") were only
required by some i386 PC clones without native FPU support.
Dropping this code simplifies the removal of the no_legacy cfg which
will be done by a future change.
BUG=b:223443221
TEST=crosvm run kernel
TEST=crosvm run --bios u-boot.rom --disk kernel
Change-Id: I7b71bd6799759ac3d35be4eb9e157d4eedd9f0c5
Signed-off-by: Alistair Delva <adelva@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3510981
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
Previous pcie cfg mmio is predefined as constand to avoid conflict with pci mmio,
this has two issues:
a. The size of pcie cfg mmio is limited to 64MB, so the max pci bus number is 64.
This isn't ennough for vfio-pci device, as such device's bus number is same as
host bus number, it may be above 64.
b. In manatee, CrOS may be required to have the same pcie cfg mmio base and size
as host.
So this commit add a parameter and let user could specify pcie cfg mmio base and
size. Then the guest memory layout will be adjusted to avoid conflict between
guest ram and pci low mmio.
BUG=b:197877871
TEST=run crosvm with --pcie-ecam=xxxx,xxxx, check vm's memory layout and pcie
ECAM function
Change-Id: I22cf7e2b3f01ab3f48dff9f5246cb1c24faa9703
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3305948
Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Junichi Uekawa <uekawa@chromium.org>
Commit-Queue: Daniel Verkamp <dverkamp@chromium.org>
When pcie cfg mmio and pci low mmio address could be specified by user,
guest memory layout will be changed to avoid conflict between guest ram,
and pci mmio below 4G. So this commit changes them from constant to
variables, the default value is prefined constand value, but it could
be changed later.
BUG=b:197877871
TEST=tools/presubmit
Change-Id: I5ad1f9d6a050d83ea16a53b926d1fadfac1ed75d
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3305947
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: Daniel Verkamp <dverkamp@chromium.org>
Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
Reviewed-by: Junichi Uekawa <uekawa@chromium.org>
By default PCIE config mmio is above pci low mmio, and they are adjacent.
When user could specify pcie config mmio address and size, the specified
address range will be highly overlap with pci low mmio or guest memory,
then it will split pci low mmio or guest memory. Finally three memory
regions exist in the below 4G space: guest ram, pci low mmio and
pcie config mmio.
In order to simplify memory space management, this commit move pcie
config mmio into pci low mmio, and pcie config mmio is reserved from
pci low mmio at the beginning. In this way, only guest ram and pci
low mmio exist in below 4G space.
BUG=None
TEST=boot a vm and check memory layout below 4G.
Change-Id: I0b253b7bf7fb0287a27a88b34ee28b0a0bd2d172
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3578016
Commit-Queue: Daniel Verkamp <dverkamp@chromium.org>
Reviewed-by: Junichi Uekawa <uekawa@chromium.org>
Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
Tested-by: kokoro <noreply+kokoro@google.com>
Now expose running pythcial CPU's max frequency to vCPU to allow intel_
pstate driver to set different CPU priority for task rebalance.
With different CPU priority, ITMT scheduling can really work in Guest.
And remove HWP and ITMT CPUID support from host-cpu-topology.
BUG=b:225375705
TEST=Set `--itmt` and check /proc/sys/kernel/sched_itmt_enabled
Change-Id: I4aa712929fe23b760d8692fed1a55992d1868fc0
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3610842
Commit-Queue: Junichi Uekawa <uekawa@chromium.org>
Reviewed-by: Junichi Uekawa <uekawa@chromium.org>
Tested-by: kokoro <noreply+kokoro@google.com>
Each vcpu has a vcpu->MsrDev file mapping. Instead of trying to create
an instance at first use, just keep an empty map in the beginning.
BUG=b:215297064
TEST=boot volteer-manatee
Change-Id: Ic5a63b0427a6441f190da3917b5f272bbb8ec778
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3611369
Commit-Queue: Junichi Uekawa <uekawa@chromium.org>
Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
Tested-by: kokoro <noreply+kokoro@google.com>
Originally, crosvm expose some HWP related CPUID under
'host-cpu-topology', now this is moved under 'itmt' flag.
Before the 'itmt' option is set in initramfs, this may break some freq
related sysfs check. So fix this compatibility issue.
BUG=b:225375705
TEST=boot brya and check cpuinfo_max_freq under sysfs
Change-Id: Iaf7f1590717c12b166d41a0e410a8fd6f605f318
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3609238
Reviewed-by: Lepton Wu <lepton@chromium.org>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
Commit-Queue: Junichi Uekawa <uekawa@chromium.org>
Reviewed-by: Junichi Uekawa <uekawa@chromium.org>
This provides at least a minimal one-line description to show what each
crate is about.
BUG=None
TEST=tools/cargo-doc
Change-Id: I26732e8c29062e622d5be09bdc120a49d564b9fd
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3630422
Reviewed-by: Dennis Kempin <denniskempin@google.com>
Commit-Queue: Daniel Verkamp <dverkamp@chromium.org>
Tested-by: kokoro <noreply+kokoro@google.com>
No functional changes.
Add trait changes to allow upstreaming hypervisor implementations. This
change differentiates between the hypervisor related data structures
from the VM specific actions to take. The format chosen is using a FnMut
that gets passed to hypervisor handler which contains the VM specific
actions.
BUG=b:213150327
TEST=Compiled crosvm.
Change-Id: I05fde5ff3d6b5f42684c7bfe8a135b6805c9dc06
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3606975
Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: Vaibhav Nagarnaik <vnagarnaik@google.com>
Add support for injecting an ACPI sleep button event using the command
line. Upon receiving crosvm sleep command, emulate vPM1 accordingly and
trigger vSCI to the guest if ACPI fixed sleep button event is enabled.
Additionally do not mask the ACPI sleep button event in FADT flags for
the guest anymore. Quoting ACPI specification regarding the sleep button
flag: "If the system does not have a sleep button, this value would be
“1” and no sleep button device would be present".
BUG=b:194391015
TEST=Boot the VM, issue "crosvm sleepbtn /run/vm/vm.<hash>/crosvm.sock",
check guest /sys/firmware/acpi/interrupts/ff_slp_btn counter and if vSCI
was injected. With some additional changes (e.g. acpid on the guest)
suspend guest by issuing sleepbtn command from the host.
Change-Id: Ie50a3a781ba4fbfa04da75186fb5549919a5bd68
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3602867
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
Commit-Queue: Grzegorz Jaszczyk <jaszczyk@google.com>
This reverts commit e93b16cefc.
Reason for revert: breaks starting VMs with less than 256 MB of memory (b/230653701)
Original change's description:
> x86_64: Redesign MTRR setting
>
> Currently MTRR setting is: the default cache type is write back and the
> pci low mmio range is uncache, then guest memory is WB by default, but
> pci high mmio and the gap between ram end and pci start below 4G are WB
> also, this part is wrong. In order to fix it, var mtrr should be used to
> set pci high mmio as uncache, but pci high mmio is too large to have
> enough var mtrrs.
>
> This commit change MTRR setting as: the default cache type is uncache,
> and the guest memory is WB. So memory range below 4G and above 4G are
> passed into setup_msrs(). And the variable MTRR registers are limited
> and have base and length requirement, so guest memory size is aligned
> to 256MB to avoid MTRR failure.
>
> BUG=None
> TEST=check guest mtrr setting with different guest memory size
>
> Change-Id: I4c18e83ce5e7fac9ac1bf6e174116a69924184ac
> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3578015
> Tested-by: kokoro <noreply+kokoro@google.com>
> Reviewed-by: Junichi Uekawa <uekawa@chromium.org>
> Commit-Queue: Junichi Uekawa <uekawa@chromium.org>
Bug: None
Change-Id: If183f028da2081ccedbbdc847311cf12081e569d
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3612468
Reviewed-by: Junichi Uekawa <uekawa@chromium.org>
Reviewed-by: Dennis Kempin <denniskempin@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Now the File descriptors aren't stored in MsrHandlers level, for every
passthrough handler, the fd will be refresh in MsrHandlers level.
This can't avoid much File descriptors creation. Fix this error.
BUG=b:225375705
TEST=Set `--userspace-msr=0x1a2,type=r,action=pass,from=cpu0`
Change-Id: I2c67a5c257f545c6469fc71d8b53606256af22c0
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3606974
Reviewed-by: Junichi Uekawa <uekawa@chromium.org>
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: Junichi Uekawa <uekawa@chromium.org>
With Intel Turbo Boost Max Technology 3.0, (ITMT), the maximum turbo
frequencies of some cores in a CPU package may be higher than for the
other cores in the same package. In that case, make the scheduler prefer
to run tasks on the CPUs with higher max turbo frequencies, to achieve
better performance.
When vCPUs 1:1 map to pCPUs, ITMT scheduling feature can benefit
performance of Guest. So when user sets `--itmt`, crosvm will check if
`--host-cpu-topology` is set or if `--cpu-affinity` is set for 1:1
mapping.
In kernel, ITMT scheduling feature depends on intel_pstate driver and
ACPI CPPC support.
To setup intel_pstate driver and pass CPPC capability check, we need
emulate related MSRs in userspace:
- MSR_HWP_CAPABILITIES and MSR_TURBO_RATIO_LIMIT: intel_pstate driver
only needs to read. So we passthrough them to Guest. But please note,
to be compatible with the configuration in initramfs, use `FromCPU0`
Temporarily.
- MSR_PM_ENABLE and MSR_HWP_REQUEST: they are MSRs to control HWP.
When intel_pstate driver is initializing, the driver will close/open
HWP by writing into MSR_PM_ENABLE, and the driver also needs to set
performance policy by writing some hints into MSR_HWP_REQUEST.
Note that we don't want Guest's behavior to affect the performance
control of the host, so use 'emulate' handler for them.
- MSR_PLATFORM_INFO: this MSR is emulated in kernel with a fault value
by default. intel_pstate doesn't want this fault value, so we ask
this MSR to exit to userspace and give it a real value.
- MSR_IA32_PERF_CTL: intel_pstate driver use this MSR to set the min
pstate in the initialization. So use 'emulate' handler for this MSR.
Since of `FromCPU0` setting of MSR_HWP_CAPABILITIES, ITMT scheduling
will set the same priority for each core so optimization will not work.
BUG=b:225375705
TEST=Set `--itmt` and check /proc/sys/kernel/sched_itmt_enabled
Change-Id: Icfa85ffa15c3b977c3b62a1f8a379c4c2f5fc49d
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3575511
Commit-Queue: Zhao Liu <zhao1.liu@intel.corp-partner.google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Junichi Uekawa <uekawa@chromium.org>
Commit-Queue: Junichi Uekawa <uekawa@chromium.org>
At present, crosvm can support handle RDMSR in userspace by read MSR of
Host directly. This is the RDMSR passthrough in userpace.
This patch adds more MSR handler support, including:
- WRMSR passthrough: write the corresponding MSR of Host directly in
userspace; The control of MSR will work on host;
- RDMSR emulation: crosvm uses a dummy MSR value to let Guest reads on.
This value can be different with real MSR of Host;
- WRMSR emulation: crosvm uses a dummy MSR value to let Guest writes
into. This means the control of MSR won't really work (on Host).
BUG=b:225375705
TEST=Set `--userspace-msr=0x1a2,type=r,action=pass,from=cpu0`
Change-Id: I3276dd651464ef7b695e2ddd433793d59128af9b
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3575508
Reviewed-by: Junichi Uekawa <uekawa@chromium.org>
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: Junichi Uekawa <uekawa@chromium.org>
Currently MTRR setting is: the default cache type is write back and the
pci low mmio range is uncache, then guest memory is WB by default, but
pci high mmio and the gap between ram end and pci start below 4G are WB
also, this part is wrong. In order to fix it, var mtrr should be used to
set pci high mmio as uncache, but pci high mmio is too large to have
enough var mtrrs.
This commit change MTRR setting as: the default cache type is uncache,
and the guest memory is WB. So memory range below 4G and above 4G are
passed into setup_msrs(). And the variable MTRR registers are limited
and have base and length requirement, so guest memory size is aligned
to 256MB to avoid MTRR failure.
BUG=None
TEST=check guest mtrr setting with different guest memory size
Change-Id: I4c18e83ce5e7fac9ac1bf6e174116a69924184ac
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3578015
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Junichi Uekawa <uekawa@chromium.org>
Commit-Queue: Junichi Uekawa <uekawa@chromium.org>
Simple rename to emphasize that vcpu_ids are not KVM-specific.
Change-Id: Icaf8a5f15a83021cf48467b0b8d0042ab0ab4a92
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3586010
Reviewed-by: Dmitry Torokhov <dtor@chromium.org>
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: Steven Moreland <smoreland@google.com>
Update the GDB stub implementation to the 0.6 version of the gdbstub
crate API, attempting to preserve the current behavior as much as
possible. Hardware breakpoints and single stepping still work, but some
existing issues with software breakpoints are still present.
BUG=None
TEST=Manual
Cq-Depend: chromium:3578400
Change-Id: I522242a1a2055ecdf47b2010a615dc9e0136ebd0
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3578025
Tested-by: kokoro <noreply+kokoro@google.com>
Auto-Submit: David LeGare <legare@google.com>
Reviewed-by: Keiichi Watanabe <keiichiw@chromium.org>
Commit-Queue: Keiichi Watanabe <keiichiw@chromium.org>
The new specialized functions take IrqEdgeEvent and IrqLevelEvent
arguments, so that callers can use them directly.
BUG=None
TEST=./tools/presubmit
Change-Id: I2c1272e31f6b20eb22743b003bd23b9c1105cda6
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3548066
Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: Dmitry Torokhov <dtor@chromium.org>
