At present, host-cpu-topology won't set HT flag for vCPU.
It's reasonable to allow Guest have the same HT flag setting as Host
when set host-cpu-topology.
BUG=None
TEST=cargo build
TEST=set host-cpu-topology and check ht flag in /proc/cpuinfo
Change-Id: I116e49975ab32d37c733690bc0f0f96148fbd4f6
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3314869
Reviewed-by: David Stevens <stevensd@chromium.org>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
Commit-Queue: Daniel Verkamp <dverkamp@chromium.org>
At present, if no_smt is set, the cpus of Guest still has the HT flag.
To fix this issue, won't set HT flag in Guest's CPUID if no_smt is set.
BUG=None
TEST=cargo build
TEST=set no_smt and check if there's HT flag in /proc/cpuinfo
Change-Id: I8a986867f272face39253b523462dc8a26ab479c
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3314868
Reviewed-by: David Stevens <stevensd@chromium.org>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Mattias Nissler <mnissler@chromium.org>
Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
Commit-Queue: Daniel Verkamp <dverkamp@chromium.org>
At present, when set host-cpu-topology option, the Guest still can't
get the hybrid information.
Now, for ADL, the hybrid related info is needed. These info include the
hybrid part flag (bit 15) in leaf 7 of CPUID, the core type and native
model id in leaf 1A of CPUID.
BUG=None
TEST=cargo build
TEST=Check the CPUID dump of Guest and Host
Change-Id: Icc03bc50160fdffc221e992d90225e7ed8081e8d
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3314867
Reviewed-by: David Stevens <stevensd@chromium.org>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
Commit-Queue: Daniel Verkamp <dverkamp@chromium.org>
The correct offset for the reset value in FADT is 128.
BUG=b:3169569
TEST=Build and boot.
Change-Id: If8bb9dc4218261464ce6100456c1386c3abb3936
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3336217
Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: Dmitry Torokhov <dtor@chromium.org>
Seems like it's not used anymore.
BUG=None
TEST=cargo test --features=direct # has less warnings.
Change-Id: Id53f89a89c8e2aa8755394503aac8e773e785c54
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3327806
Auto-Submit: Junichi Uekawa <uekawa@chromium.org>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
Commit-Queue: Junichi Uekawa <uekawa@chromium.org>
In order to comply with kernel E820Type definition and make code more
readable, this commit changes E820Type from constants to enum.
BUG=None
TEST=tools/presubmit
Change-Id: I514a3f71c734305c19cebbca6844f09d1fb16dab
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3314866
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Junichi Uekawa <uekawa@chromium.org>
Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
Commit-Queue: Daniel Verkamp <dverkamp@chromium.org>
Since _OSC is added, OS could negotiate any pcie features with firmware
through _OSC, so remove "pcie_ports=native" parameter from command line.
BUG=b:197877871
TEST=check pcie native hotplug compability in VM
Change-Id: Iba363aa0d5c6acaf61d72ed9cc4697677f9ace6c
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3305946
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
Commit-Queue: Daniel Verkamp <dverkamp@chromium.org>
OS call acpi _OSC method to request control for PCIE natvie features like
pcie hotplug, pcie advanced error report, pcie PME. But currently crosvm
lack of _OSC method, so OS couldn't enable these pcie features.
This commit add _OSC method, enable pcie hotplug and pcie cap structure
control, but disable SHPC hotplug, pcie PME and pcie AER.
BUG=b:197877871
TEST=Check pcie hotplug capability in VM
Change-Id: If4b6c8026c312ebfdeb18df7c0673571e3e9b631
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3305945
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
Commit-Queue: Daniel Verkamp <dverkamp@chromium.org>
Intel acpi method reads PCIEBAR Base Address Register in host bridge to
get the pcie config mmio base address. This commit emulates this
register, so the acpi method could get the right information.
BUG=b:197877871
TEST=Verify this regsiter's value in a vm
Change-Id: I93bf8e678acc0e085b102a2eb3a88cbf466aed78
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3305944
Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: Junichi Uekawa <uekawa@chromium.org>
In order to enable pcie enhanced configurtion access mechanism in kernel,
acpi mcfg table is mandatory. So kernel could know the base and size of
pcie enhanced configuration access mmio.
BUG=b:197877871
TEST=Boot a vm and r/w pci config regiser through pcie ECAM
Change-Id: Icecedba3f31cd94bed76e48932c5e77f56effb9c
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3305943
Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: Junichi Uekawa <uekawa@chromium.org>
Since PciRoot has been modified into Arc<Mutex<>>, RunnableLinuxVm->root_config
could be changed from PciConfigArch to PciRoot also, this could simplify code
and reduce two functions from PciConfigArch.
BUG=b:197877871
TEST=tools/presubmit
Change-Id: Ibc18587900d6f8259ac1d6f8fe7b3ea4fedad07e
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3305942
Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: Junichi Uekawa <uekawa@chromium.org>
Now that we have wired up PCI reset and exposed it via ACPI reset
register we no longer need to force resetting via keyboard port.
BUG=b:3169569
TEST=Reboot mantee board
Change-Id: I4bc02909199b3f519993794e28ed742432ebd64b
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3317156
Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: Dmitry Torokhov <dtor@chromium.org>
Instead of returning 0 for both shutdown and reset/reboot, let's have
shutdown continue returning 0, but reset will now return 32 exit code,
so that callers will have an option to handle this case differently.
BUG=b:3169569
TEST=Examine crosvm exit codes when resetting and shutting down VM
Change-Id: I2c7c11b7f8c8528744f7e25e5d17c6fa9810f409
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3316835
Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: Dmitry Torokhov <dtor@chromium.org>
This will allow guest OS to issue reset requests via ACPI methods.
BUG=b:3169569
TEST=Build and boot.
Change-Id: I6d29422f962c21a2e513cb4da78515e31468a1e5
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3316834
Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: Dmitry Torokhov <dtor@chromium.org>
This is a bit of a hack, but crosvm does not support overlapping IO/MMIO
regions, so we have to handle reset register in PciConfigIo handler
(which covers 0xcf8 - 0xcff range) instead of installing a dedicated
reset handler separate from PCI root handler.
BUG=b:3169569
TEST=Try rebooting Manatee booted with "reboot=p"
Change-Id: I79991f456d4aaaab2c904e312996208aa72ab6ec
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3316833
Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: Dmitry Torokhov <dtor@chromium.org>
Reserved 64MB mmio space for pcie enhanced configuration access,
and added it into mmio_bus with PciConfigMmio.
Now pci_root will be added into PciConfigIo and PciConfigMmio, so
Arc<Mux<pci_root>> is used.
BUG=b:197877871
TEST=tools/presubmit
Change-Id: Ic90a4cc3dfb00b09358478e129cc8a16e91012c6
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3305941
Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Junichi Uekawa <uekawa@chromium.org>
Commit-Queue: Junichi Uekawa <uekawa@chromium.org>
Hex memory regions usually are better expressed with 4 digits as one
compound.
BUG=b:188011323
TEST=None
Change-Id: Ic42fcbb6fd8c4ada5f0fb18c2ff41e3dbffb3408
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3312863
Commit-Queue: Junichi Uekawa <uekawa@chromium.org>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
Instead of open coding a loop, use any() method to check if we have
matching entries.
BUG=None
TEST=./tools/presubmit
Change-Id: Ib1fe7e65436bc3c8cca99be69855eb0ebc3cf096
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3313842
Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: Dmitry Torokhov <dtor@chromium.org>
The pci_irqs list contains an entry for each PCI device, but IRQ numbers
may be reused, so the MADT would contain duplicate interrupt override
entries in this case. This doesn't cause a problem in practice (the
duplicates are all identical and the guest kernel does not complain),
but it makes sense to remove the duplicates and only add a single
IOAPIC interrupt override entry per unique IRQ number.
BUG=b:207551552
TEST=x86_64 guest kernel only has 4 INT_SRC_OVR logs in dmesg
Change-Id: Iba4c57ca93d4be6c21e087b2f3f416fe022e8d35
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3315408
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: Daniel Verkamp <dverkamp@chromium.org>
Reviewed-by: Dmitry Torokhov <dtor@chromium.org>
Basic functionality works with a purely ACPI-based boot (no MPTable),
but something is still missing in the ACPI tables for describing the
full interrupt routing configuration. The guest kernel complains:
virtio-pci 0000:00:01.0: can't derive routing for PCI INT A
virtio-pci 0000:00:01.0: PCI INT A: no GSI
Restore the acpi=noirq option for now until we fill out the ACPI IRQ
descriptors correctly; this was a cleanup only and not required to fix a
bug.
This reverts commit cb464a7c08.
BUG=None
TEST=Boot Crostini; no interrupt routing failures in dmesg
Change-Id: Ib73c5749b48134124b3ebcb472706f087e8a85a2
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3315226
Reviewed-by: Dennis Kempin <denniskempin@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: Daniel Verkamp <dverkamp@chromium.org>
Now that we provide a correct MADT ("APIC" table ID), there is no need
to override the kernel ACPI option that made it ignore these tables.
BUG=None
TEST=Boot crosvm with setup_mptable() call removed, ACPI only
Change-Id: I9f4589738462c5693f151f60180c79d054a9084d
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3313841
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: Daniel Verkamp <dverkamp@chromium.org>
Reviewed-by: Dmitry Torokhov <dtor@chromium.org>
Reviewed-by: Dennis Kempin <denniskempin@google.com>
KVM's irqchip emulation provides the traditional PC-style pair of 8259
PICs, so report this by setting the appropriate flag in the MADT (APIC)
table.
BUG=b:207551552
TEST=Boot crosvm with setup_mptable() call removed
Change-Id: Ib5adf7ac717156deb3cd19d74873c9745ae826ec
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3313840
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: Daniel Verkamp <dverkamp@chromium.org>
Reviewed-by: Dmitry Torokhov <dtor@chromium.org>
Add interrupt redirection entries to MADT so that the legacy pin-based
interrupts are correctly reported as level triggered. This matches the
entries in the existing MPTable, but those are not availble when booting
with OVMF, which only provides ACPI tables.
This fixes an issue where USB device sharing was failing in some cases
when booted with ACPI only, since our xhci controller emulation only
supports pin-based interrupts (not MSI-X) and would not work correctly
when the guest incorrectly treated its IRQ as edge triggered.
BUG=b:207551552
TEST=Start crosvm with setup_mptable() call removed
TEST=Share USB device when booted with ACPI via OVMF
Change-Id: Id3e4ff5ba9587aadbeadbcc8eceaa771c4c2d5df
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3312577
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: Daniel Verkamp <dverkamp@chromium.org>
Reviewed-by: Dmitry Torokhov <dtor@chromium.org>
This function doesn't need to consume the pci_irqs vector, just iterate
over it.
BUG=None
TEST=tools/presubmit
Change-Id: Ibb66fa6ab8c45f58eeb89b976bcfc57e00d718a1
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3313996
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: Daniel Verkamp <dverkamp@chromium.org>
Reviewed-by: Dmitry Torokhov <dtor@chromium.org>
Reviewed-by: Dennis Kempin <denniskempin@google.com>
PcieRootPort implement hotplug_bus trait, it should be added into
RunnableLinuxVm->hotplug_bus, so create pcie root port when
RunnableLinuxVm->hotplug_bus is ready.
Many hotplug bus may exist, when a hotplug device is added, is_match()
should be called on each hotplug bus before attach that device to
the bus.
BUG=b:185084350
TEST=Boot a vm with passthrough device and check its function
Change-Id: I89dbc091f336b3f9d0435b52963f7cf62d408a67
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/2955570
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: Daniel Verkamp <dverkamp@chromium.org>
Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
There were not too many cases here. This fixes:
- comparison_chain
- wrong_self_convention
- upper_case_acronyms
- from_over_into
- let-and-return
The collapsible_if check is moved to the permanently
allowed checks. The cases we do have improve
readability or semantics.
BUG=chromium:908640
TEST=Kokoro
Change-Id: I6e905d08e2a87aa0862d4d1cf5ff57b60e95fa7d
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3278776
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: Dennis Kempin <denniskempin@google.com>
Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
Use the anyhow crate to provide ad-hoc errors with context. This removes
the large, manually-updated enum, which we never use programmatically
anyway (error messages are printed in human-readable form and otherwise
not matched against).
BUG=b:190433480
TEST=cargo build
TEST=./test_all
Change-Id: Ia7b90b33774d4031054b346d650861d3105044ee
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3105436
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: Daniel Verkamp <dverkamp@chromium.org>
Reviewed-by: Chirantan Ekbote <chirantan@chromium.org>
Original reason for revert: Causes crosvm to not start on AMD based devices b/204222491
Fixed by clamping the maximum physical address to 64 TiB, which is the
largest physical address supported by x86-64 Linux with only 4-level
page tables enabled.
In addition, the high MMIO region size calculation has been split into a
separate function, get_high_mmio_size(), and an off-by-one error in the
size calculation was fixed.
Original change's description:
> Devices: Allocate non pci bar mmio at top of HighMmio
>
> Some devices like virtio-pmem, intel host bridge need private mmio, these private
> mmio isn't exposed to Vm through pci bar, and crosvm use mmio allocation interface
> to allocate them, so guest OS pci bus driver couldn't detect them, and once guest
> OS reallocate pci mmio, these private mmmio could be assigned to pci device bar.
> then resource conflict happens.
>
> This patch allocates these non pci bar mmio at the top of HighMmio, since HighMmio
> is large enough and OS allocates pci mmio from low to high. So these non pci bar
> mmio won't conflict with pci bar.
>
> BUG=b:199442120
> BUG=b:185084350
> TEST=crosvm run --pmem-device xxxx
>
> Change-Id: I615d7901d595dd46ba6362f88b71d96baa9c4c8f
> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3184549
> Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
> Tested-by: kokoro <noreply+kokoro@google.com>
> Commit-Queue: Daniel Verkamp <dverkamp@chromium.org>
This is a reland of https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3184549
BUG=b:199442120
BUG=b:185084350
TEST=Crostini starts on grunt (AMD device)
TEST=crosvm run --pmem-device rootfs -p 'root=/dev/pmem0' kernel
Change-Id: I7c93f7132dbfbc3f38ecbfa0504b59214a1eb6bf
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3251788
Reviewed-by: Xiong Zhang <xiong.y.zhang@intel.corp-partner.google.com>
Reviewed-by: Dennis Kempin <denniskempin@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: Daniel Verkamp <dverkamp@chromium.org>
This change contains the results of running
./tools/contib/cargo_refactor.py
This will break the next uprev, and needs to be synchronizized
with the corresponding ebuild changes in https://crrev.com/c/3248925
BUG=b:195126527
TEST=./tools/run_tests
Change-Id: Ied15a1841887bb8f59fba65b912b81acf69beb73
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3248129
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: Dennis Kempin <denniskempin@google.com>
Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
This reverts commit 9557588786.
Reason for revert: Causes crosvm to not start on AMD based devices b/204222491
Original change's description:
> Devices: Allocate non pci bar mmio at top of HighMmio
>
> Some devices like virtio-pmem, intel host bridge need private mmio, these private
> mmio isn't exposed to Vm through pci bar, and crosvm use mmio allocation interface
> to allocate them, so guest OS pci bus driver couldn't detect them, and once guest
> OS reallocate pci mmio, these private mmmio could be assigned to pci device bar.
> then resource conflict happens.
>
> This patch allocates these non pci bar mmio at the top of HighMmio, since HighMmio
> is large enough and OS allocates pci mmio from low to high. So these non pci bar
> mmio won't conflict with pci bar.
>
> BUG=b:199442120
> BUG=b:185084350
> TEST=crosvm run --pmem-device xxxx
>
> Change-Id: I615d7901d595dd46ba6362f88b71d96baa9c4c8f
> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3184549
> Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
> Tested-by: kokoro <noreply+kokoro@google.com>
> Commit-Queue: Daniel Verkamp <dverkamp@chromium.org>
Bug: b:199442120
Bug: b:185084350
Change-Id: Ida1369bf0b70782633b1073ceef50e1bab108f55
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3248906
Bot-Commit: Rubber Stamper <rubber-stamper@appspot.gserviceaccount.com>
Commit-Queue: Dennis Kempin <denniskempin@google.com>
Rust bindgen now supports --allowlist and --blocklist option names as of
https://github.com/rust-lang/rust-bindgen/pull/1990 - use them in the
various bindgen invocations in scripts and comments.
BUG=b:178821708
TEST=../dev/contrib/search_blocked_words.sh unblocked_terms.txt
Change-Id: I9797f049999a01ab2c41617823463236b4d03cbb
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3243012
Reviewed-by: Dennis Kempin <denniskempin@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: Daniel Verkamp <dverkamp@chromium.org>
Some devices like virtio-pmem, intel host bridge need private mmio, these private
mmio isn't exposed to Vm through pci bar, and crosvm use mmio allocation interface
to allocate them, so guest OS pci bus driver couldn't detect them, and once guest
OS reallocate pci mmio, these private mmmio could be assigned to pci device bar.
then resource conflict happens.
This patch allocates these non pci bar mmio at the top of HighMmio, since HighMmio
is large enough and OS allocates pci mmio from low to high. So these non pci bar
mmio won't conflict with pci bar.
BUG=b:199442120
BUG=b:185084350
TEST=crosvm run --pmem-device xxxx
Change-Id: I615d7901d595dd46ba6362f88b71d96baa9c4c8f
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3184549
Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: Daniel Verkamp <dverkamp@chromium.org>
At present the Guest generates its own CPU topology. To mitigate
cross-hyperthread speculative execution side channel attacks, allow
Guest to use mirror CPU topology of Host is needed for future scheduling
optimization.
Add a config option "--host-cpu-topology" to ask the vCPU number to be
identical to physical CPUs, and make the vCPU has the same APIC ID in
MADT and CPUID as the corresponding physical CPU. The same APIC ID can
ensure the same topology.
"--host-cpu-topology" requires vCPU number must equal to pCPU number,
and it has the default vCPU number setting, which equals to pCPU number.
"--host-cpu-topology" also defaultly sets CPU affinity for each vCPU to
the pCPU which has the same processor ID, like 1=1:2=2:3=3:4=4, so that
the vCPU and its corresponding pCPU will have the same processor ID and
the same APIC ID. User can't set CPU affinity if "--host-cpu-topology"
was set.
BUG=b:197875305
TEST=Set "--host-cpu-topology" option and check Guest's /proc/cpuinfo,
lscpu, CPUID for different vCPU
Change-Id: Ibc4eb10649e89f43b81bde6d46d6e0e6c7234324
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3217035
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: Chirantan Ekbote <chirantan@chromium.org>
Reviewed-by: Chirantan Ekbote <chirantan@chromium.org>
At present the Guest use the cpu id (enum number) as the APIC ID in vCPU
CPUID and set the different topology with pCPU.
To support the feature vCPU has the same topology as pCPU, vCPU need the
same APIC ID as pCPU. So let vCPU can use the APIC ID from pCPU in
vCPU's CPUID and keep pCPU's topology related information (include CPU
count and topology mask) unchanged.
Now this change is a preliminary preparation and doesn't work.
Additional feature options and corresponding CPU number and CPU affinity
settings are still required.
BUG=b:197875305
TEST=cargo build
TEST=./test_all
Change-Id: I04150ac6c35534d0ff56667b01f448da2ca9f9fc
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3217034
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: Chirantan Ekbote <chirantan@chromium.org>
Reviewed-by: Chirantan Ekbote <chirantan@chromium.org>
Reviewed-by: David Stevens <stevensd@chromium.org>
At present the Guest use the cpu id (enum number) as the APIC ID in
Guest MADT.
To support the feature vCPU has the same topology as pCPU, vCPU need
the same APIC ID as pCPU. So let Guest MADT can use the APIC ID from
Host is needed.
Now this change is a preliminary preparation and doesn't work. The APIC
ID related changes for vCPU CPUID are still required.
BUG=b:197875305
TEST=cargo build
TEST=./test_all
Change-Id: I0e7dfba8cd57fefd85b7d7e37de3bb9935ff19ee
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3217033
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: Chirantan Ekbote <chirantan@chromium.org>
Reviewed-by: Chirantan Ekbote <chirantan@chromium.org>
Reviewed-by: David Stevens <stevensd@chromium.org>
With vfio pci device hotplug, bus->devices will be inserted and removed at
runtime in different vcpu threads, so mutex should be used to protect it.
Both each vcpu thread and pci_root share mmio_bus and io_bus, so use Arc
for mmio_bus and io_bus. But pci_root is inserted into io_bus for pci cfg io,
in order to resolve reference loop and memory leak, weak is used for
pci_root.mmio_bus and pci_root.io_bus.
BUG=b:174705596
TEST=boot a vm and check its function
Change-Id: I7b3e63db76a90bc3873619b4d80a66db741ce78f
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3184724
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: Chirantan Ekbote <chirantan@chromium.org>
Reviewed-by: Chirantan Ekbote <chirantan@chromium.org>
Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
This was an oversight from the previous commit to pass the kernel
command line to a bios.
BUG=b:200208446
TEST=Observe pstore working across reboots
Change-Id: Ie93cc3399000a83099d396f4dde1da9d835704be
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3197732
Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
Reviewed-by: Dennis Kempin <denniskempin@google.com>
Reviewed-by: Noah Gold <nkgold@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: Dennis Kempin <denniskempin@google.com>
Auto-Submit: Tom Cherry <tomcherry@google.com>
Before we call build_vm we are creating devices and there is no reason
to assume those have to be PCI only. In preparation for VFIO platform
device support, add super trait which allows to pass generic device
structure around and still be able get back to our original type.
BUG=b:185504618
TEST=manatee PCI device passthrough boots/works
Change-Id: I500f44af430f5f06299f20fc4ca17ca008a7e0c5
Signed-off-by: Tomasz Nowicki <tn@semihalf.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/2961210
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: Tomasz Nowicki <tnowicki@google.com>
Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
This enables the bios to read kernel command line parameters
from crosvm and pass them to the kernel that it loads.
BUG=b:195323844
TEST=pass --params through uboot to Linux
Change-Id: I306bb16421393583edc8b0dbdb3198a5b3cc0377
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3140277
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: Tom Cherry <tomcherry@google.com>
Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
Replace the uses of read_struct() and read_struct_slice() with the
safe DataInit::from_reader() implementation.
BUG=b:197263364
TEST=./test_all
TEST=Boot bzImage kernel
TEST=Boot raw ELF kernel extracted with extract_vmlinux
Change-Id: I80f98243bfb58a7ae93e1686bc4d92b0cd485cda
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3108249
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: Daniel Verkamp <dverkamp@chromium.org>
Reviewed-by: Chirantan Ekbote <chirantan@chromium.org>
Tree-wide cleanup of new clippy warning in Rust 1.54 that warns about
needless borrows:
error: this expression borrows a reference (`&...`) that is
immediately dereferenced by the compiler
https://rust-lang.github.io/rust-clippy/master/index.html#needless_borrow
BUG=b:197251702
TEST=bin/clippy # with rust-toolchain = 1.54.0
Change-Id: Ib702ec524d4623d264a00ec11dbc2150c411a67b
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3108321
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Allen Webb <allenwebb@google.com>
Reviewed-by: Tomasz Jeznach <tjeznach@chromium.org>
Reviewed-by: Chirantan Ekbote <chirantan@chromium.org>
Commit-Queue: Daniel Verkamp <dverkamp@chromium.org>
Add necessary kernel cmdlines for aarch64.
Adjust PCI address to make room for ramoops on aarch64.
Move the code from x86_64 to common places.
BUG=b:153934386
TEST=vm_pstore_dump
Change-Id: I8f92a7fd04a49afd7e8be9e7cf1901ef70b88d65
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3103131
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
Reviewed-by: Kansho Nishida <kansho@chromium.org>
Commit-Queue: Ryo Hashimoto <hashimoto@chromium.org>
Device implement HotPlugBus trait could notify hotplug event into
guest, and such device should be added into RunnableLinuxVm, so it
could be used at device plug in and plug out.
BUG=b:185084350
TEST=Boot a guest with and without passthrough device
Change-Id: I9497f61312582483090ff708d0f37b97d7303811
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/2954673
Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: Daniel Verkamp <dverkamp@chromium.org>
When a vfio pci device is added through hotplug in, it should be configured
at runtime and added into pci_root->devices tree, so pci_root is added
into linux.
BUG=b:185084350
TEST=Boot a guest with and without passthrough device
Change-Id: Ibcb5f4a849134f64fbceeac645bebd80d6ca72d5
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/2954672
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: Daniel Verkamp <dverkamp@chromium.org>
Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
Move the definitions of SerialHardware, SerialParameters and SerialType
to the devices crate so that they'll be available for code in the
devices crate as well.
BUG=b:195495971
TEST=cargo test
Change-Id: Ieb711bdb18a8afdb28cac262a3355739604d4607
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3096439
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: Keiichi Watanabe <keiichiw@chromium.org>
Reviewed-by: Chirantan Ekbote <chirantan@chromium.org>
Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
BUG=b:191784608
TEST=Build and run atest in Android tree
Cq-Depend: chromium:3073700
Change-Id: I5fcfa166caf8c5a5f759a8f62ef78a293db95f1a
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3071900
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andrew Walbran <qwandor@google.com>
Reviewed-by: Dennis Kempin <denniskempin@google.com>
Commit-Queue: Dennis Kempin <denniskempin@google.com>
This flag is intended to be used to delay making a VM's RT VCPUs
RT until "make_rt" is called, in order to avoid boot time
regressions with RT.
BUG=b:142777321
TEST="grep policy /proc/<pid of rt vcpu>/sched" to make sure RT vcpu
isn't RT until "make_rt".
Change-Id: I1b9132e11f0acc626434c60cecc2f4afe350961a
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/2703224
Auto-Submit: Suleiman Souhlal <suleiman@chromium.org>
Reviewed-by: Chirantan Ekbote <chirantan@chromium.org>
Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
Reviewed-by: Dylan Reid <dgreid@chromium.org>
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: Suleiman Souhlal <suleiman@chromium.org>
The devices to be notified on resume are unrelated to the functionality
of Bus, which is looking up devices in an address space. Additionally,
each Bus instance had its own list of devices to notify, although in
practice, only the one in the I/O bus was used.
Move the resume_notify_devices list into RunnableLinuxVm instead.
BUG=None
TEST=Boot Crostini on x86 and arm
Change-Id: I72c629c6d6589c4a9350831c8a076c5c0c9f9aeb
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3043489
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: Daniel Verkamp <dverkamp@chromium.org>
Reviewed-by: Tomasz Jeznach <tjeznach@chromium.org>
