PCI virtual configuration space is a set of virtual registers similar to
PCI configuration space, but for the guest to configure the hypervisor.
One use case is to facilitate ACPI forwarding at API level.
BUG=b:194390621
TEST=builds
Change-Id: I7902d8f589d19426c8b81629722abbf5c68a905a
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3344575
Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: Victor Ding <victording@chromium.org>
Auto-Submit: Victor Ding <victording@chromium.org>
This reverts commit d2d66bc0a4.
Reason for revert: It turns out that adding the first page to the pool
of memory managed by the MMIO allocator has undesired consequences
since crosvm will actually use it for MMIO regions. The first page
has special semantics in other code though, and thus we get stray
accesses to this region, with hard-to-predict consequences.
BUG=b:188011323
TEST=cq
Original change's description:
> system_allocator: allow more than one region to be in the pool
>
> Allows crosvm-direct to have 0-0xfff regions to be mapped.
>
> limitations: Only the first regions gets reflected in the
> pool_base/pool_size.
>
> BUG=b:188011323
> BUG=b:184815519
> TEST=build
>
> Change-Id: I9da3cb2b8d5611068f9323d6ebf62f44162838b4
> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3450017
> Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
> Tested-by: kokoro <noreply+kokoro@google.com>
> Commit-Queue: Junichi Uekawa <uekawa@chromium.org>
Bug: b:188011323
Bug: b:184815519
Change-Id: Ib42b3007662a7a49ad876b83a01f1bb88d09d5f7
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3497136
Reviewed-by: Keiichi Watanabe <keiichiw@chromium.org>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Mattias Nissler <mnissler@chromium.org>
Commit-Queue: Mattias Nissler <mnissler@chromium.org>
Adding some conditional compilation flags so we do not need to
exclude them on each test run. None of there actually increase
the number of tests run, but gets us closer to being able
to run `cargo test --workspace`
BUG=b:218374759
TEST=./tools/presubmit --all
Change-Id: I181a84847fc09a4e1a6fb2b5f21538ebc400d607
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3453046
Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: Dennis Kempin <denniskempin@google.com>
Fixed ACPI Description Table (FADT) contains Low Power S0 Idle Capable
Flag. This commit introduces "--s2idle" argument allowing to set proper
bit in the guest FADT table. This is required to inform guest OS to use
s2idle instead of traditional S3 power mode.
BUG=b:194391015
TEST=Build crosvm and run "crosvm run --s2idle ..", dump FADT table and
confirm that proper flag was set.
Change-Id: I243bfe2cc4840278fcdbf33dcb147b2eda50856d
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3457402
Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: Grzegorz Jaszczyk <jaszczyk@google.com>
Run tests for sys_util_core, poll_token_derive and balloon_control on
windows.
Using dotfiles to disable/serialize test runs of a subset of crates does
not work well with third party crates as it forces us to commit the dot
file to the crate.
The patch modifies and uses the script that runs linux tests.
This patch also allows us to
- build/test child crate even if parent crate has disabled build/test.
- avoid building crosvm if it is not explicitly specified.
RIP short lived .windows_build_test_skip. You allowed us to run noop
kokoro tests.
Test: py .\tools\impl\test_runner.py --arch x86_64
Bug: b:215610772
Change-Id: Icc6d04ffd7c0c33d4f60aeac16fc7d23881c387d
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3459809
Reviewed-by: Dennis Kempin <denniskempin@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: Vikram Auradkar <auradkar@google.com>
io ports is a 16 bit thing, check that it is actually 16 bits and fix
the parameters.
BUG=None
TEST=read intel SDM, run crosvm test
Change-Id: I50b6d5593b0699317ac2f852836208a46240714b
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3470601
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
Commit-Queue: Junichi Uekawa <uekawa@chromium.org>
Allows crosvm-direct to have 0-0xfff regions to be mapped.
limitations: Only the first regions gets reflected in the
pool_base/pool_size.
BUG=b:188011323
BUG=b:184815519
TEST=build
Change-Id: I9da3cb2b8d5611068f9323d6ebf62f44162838b4
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3450017
Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: Junichi Uekawa <uekawa@chromium.org>
In preparation to allow multiple low memory regions to be passed on, I wanted to
make initialization simpler.
Introduce `MemRegion` struct instead of tuple to help me understand it is a base
and size.
BUG=b:188011323
TEST=build
Change-Id: Ie8b54354a25c478d5ad0a0185b7e07d28840dd87
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3439666
Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: Junichi Uekawa <uekawa@chromium.org>
The bindings need to be regenerated. Just disable warnings for now.
BUG=b:192373803
TEST=./tools/presubmit
Change-Id: Ia34638cbc20c4705631ea3693d4476137ebf8d55
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3439051
Reviewed-by: Noah Gold <nkgold@google.com>
Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: Dennis Kempin <denniskempin@google.com>
crosvm seems to be adding an extra mptable entry for irq0 that points to
a non-existent ioapic (with apic_id=0 where the ioapic's id is not 0).
The bad irq0 and valid irq0 entries are the first two listed when using
apic=debug and show_lapic=all kernel params:
```
[ 0.756044] Int: type 0, pol 0, trig 0, bus 01, IRQ 00, APIC ID 0, APIC INT 00
[ 0.764474] Int: type 0, pol 0, trig 0, bus 01, IRQ 00, APIC ID 5, APIC INT 00
```
If the bad irq0 entry exists, and if check_timer is called in io_apic.c
in the kernel, it can cause an invalid opcode exception in some kernels,
seemingly because it ends up calling find_irq_entry(-1, -1, 0) which
does a -1 index on the static "ioapics" struct in io_apic.c. It seems
like a kernel bug that such an index could happen, but this also seems
like a bad entry in mptables.
A similar irq entry exists in kvmtool, but it it's a local interrupt. If
this entry is adjusted to match then the invalid opcode kernel panic
stops.
BUG=b:211912415
TEST=ran linux image, booted fine
Change-Id: I125dd2458f86de65553577b8d1c4d1366d778de9
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3405332
Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: Colin Downs-Razouk <colindr@google.com>
The patch also adds files to skip building and testing crates on
windows. When we run
```
tools/windows/build_test.py --skip_file_name .windows_build_test_skip
```
the build/test succeeds without actually doing anything as build/test
for all crates is skipped by creating '.windows_build_test_skip'.
Bug: 213170957
Test: Ran script on downstream repo
Change-Id: Iebd2cea463ee722be4feaed88229e1fb5e9fd6c5
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3417918
Reviewed-by: Dennis Kempin <denniskempin@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: Vikram Auradkar <auradkar@google.com>
Let's pass host's processor brand string to guests, so that lscpu and
/proc/cpuinfo do not fall back to printing numeric model numbers
but rather print vendor string, such as:
Intel(R) Core(TM) i3-10110U CPU @ 2.10GHz
or
AMD Ryzen 3 3250C 15W with Radeon Graphics
BUG=None
TEST=boot zork and hatch, examine lscpu in crostini
Change-Id: I7cd3ccd4a6328695cc180ee4c13d19d2e48f3def
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3410647
Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: Dmitry Torokhov <dtor@chromium.org>
The high MMIO region of the system allocator was previously set up with
the upper limit of 2**64 - 1, but physical addresses on actual systems
are not that large. Now that pmem allocates from the upper end of the
high MMIO region, the size of the allocator actually matters.
Limit the aarch64 high MMIO allocator to the VM's physical address size
so that addresses at the end of the allocation range are usable and pmem
devices can be created on aarch64.
BUG=b:210727578
TEST=Boot with pmem device on aarch64
Change-Id: I67962c2b03f0f265349ae889c988eb69ef526f4a
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3366858
Reviewed-by: Dmitry Torokhov <dtor@chromium.org>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andrew Walbran <qwandor@google.com>
Commit-Queue: Daniel Verkamp <dverkamp@chromium.org>
Add a function that returns the size of guest physical addresses. This
wraps KVM_CAP_ARM_VM_IPA_SIZE on aarch64 and CPUID to query host
physical address size on x86_64. This replaces the phy_max_address_bits
function from x86_64, and all callers are migrated to use the new Vm
function instead.
BUG=b:210727578
TEST=check on trogdor64 with debug prints
Change-Id: I3107fe6357fcf166b7ad0e2a7c55919705da3b0c
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3364971
Reviewed-by: Dmitry Torokhov <dtor@chromium.org>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Alexandre Courbot <acourbot@chromium.org>
Reviewed-by: Andrew Walbran <qwandor@google.com>
Commit-Queue: Daniel Verkamp <dverkamp@chromium.org>
This involves two main changes:
* Protected VMs must be created with KVM_VM_TYPE_ARM_PROTECTED.
* pVM firmware is now loaded by IPA rather than memslot ID.
There are also a lot of trivial changes because the ProtectionType enum
was moved from the devices crate to the hypervisor crate.
BUG=b:209794844
TEST=Will tested manually with patched kernel and dummy firmware
Change-Id: I1dd75e20063ca4736f155292ca5f70b94664fdd9
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3330204
Auto-Submit: Andrew Walbran <qwandor@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
Commit-Queue: Daniel Verkamp <dverkamp@chromium.org>
At present, host-cpu-topology won't set HT flag for vCPU.
It's reasonable to allow Guest have the same HT flag setting as Host
when set host-cpu-topology.
BUG=None
TEST=cargo build
TEST=set host-cpu-topology and check ht flag in /proc/cpuinfo
Change-Id: I116e49975ab32d37c733690bc0f0f96148fbd4f6
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3314869
Reviewed-by: David Stevens <stevensd@chromium.org>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
Commit-Queue: Daniel Verkamp <dverkamp@chromium.org>
At present, if no_smt is set, the cpus of Guest still has the HT flag.
To fix this issue, won't set HT flag in Guest's CPUID if no_smt is set.
BUG=None
TEST=cargo build
TEST=set no_smt and check if there's HT flag in /proc/cpuinfo
Change-Id: I8a986867f272face39253b523462dc8a26ab479c
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3314868
Reviewed-by: David Stevens <stevensd@chromium.org>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Mattias Nissler <mnissler@chromium.org>
Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
Commit-Queue: Daniel Verkamp <dverkamp@chromium.org>
At present, when set host-cpu-topology option, the Guest still can't
get the hybrid information.
Now, for ADL, the hybrid related info is needed. These info include the
hybrid part flag (bit 15) in leaf 7 of CPUID, the core type and native
model id in leaf 1A of CPUID.
BUG=None
TEST=cargo build
TEST=Check the CPUID dump of Guest and Host
Change-Id: Icc03bc50160fdffc221e992d90225e7ed8081e8d
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3314867
Reviewed-by: David Stevens <stevensd@chromium.org>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
Commit-Queue: Daniel Verkamp <dverkamp@chromium.org>
The correct offset for the reset value in FADT is 128.
BUG=b:3169569
TEST=Build and boot.
Change-Id: If8bb9dc4218261464ce6100456c1386c3abb3936
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3336217
Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: Dmitry Torokhov <dtor@chromium.org>
Seems like it's not used anymore.
BUG=None
TEST=cargo test --features=direct # has less warnings.
Change-Id: Id53f89a89c8e2aa8755394503aac8e773e785c54
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3327806
Auto-Submit: Junichi Uekawa <uekawa@chromium.org>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
Commit-Queue: Junichi Uekawa <uekawa@chromium.org>
In order to comply with kernel E820Type definition and make code more
readable, this commit changes E820Type from constants to enum.
BUG=None
TEST=tools/presubmit
Change-Id: I514a3f71c734305c19cebbca6844f09d1fb16dab
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3314866
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Junichi Uekawa <uekawa@chromium.org>
Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
Commit-Queue: Daniel Verkamp <dverkamp@chromium.org>
Since _OSC is added, OS could negotiate any pcie features with firmware
through _OSC, so remove "pcie_ports=native" parameter from command line.
BUG=b:197877871
TEST=check pcie native hotplug compability in VM
Change-Id: Iba363aa0d5c6acaf61d72ed9cc4697677f9ace6c
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3305946
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
Commit-Queue: Daniel Verkamp <dverkamp@chromium.org>
OS call acpi _OSC method to request control for PCIE natvie features like
pcie hotplug, pcie advanced error report, pcie PME. But currently crosvm
lack of _OSC method, so OS couldn't enable these pcie features.
This commit add _OSC method, enable pcie hotplug and pcie cap structure
control, but disable SHPC hotplug, pcie PME and pcie AER.
BUG=b:197877871
TEST=Check pcie hotplug capability in VM
Change-Id: If4b6c8026c312ebfdeb18df7c0673571e3e9b631
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3305945
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
Commit-Queue: Daniel Verkamp <dverkamp@chromium.org>
Intel acpi method reads PCIEBAR Base Address Register in host bridge to
get the pcie config mmio base address. This commit emulates this
register, so the acpi method could get the right information.
BUG=b:197877871
TEST=Verify this regsiter's value in a vm
Change-Id: I93bf8e678acc0e085b102a2eb3a88cbf466aed78
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3305944
Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: Junichi Uekawa <uekawa@chromium.org>
In order to enable pcie enhanced configurtion access mechanism in kernel,
acpi mcfg table is mandatory. So kernel could know the base and size of
pcie enhanced configuration access mmio.
BUG=b:197877871
TEST=Boot a vm and r/w pci config regiser through pcie ECAM
Change-Id: Icecedba3f31cd94bed76e48932c5e77f56effb9c
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3305943
Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: Junichi Uekawa <uekawa@chromium.org>
Since PciRoot has been modified into Arc<Mutex<>>, RunnableLinuxVm->root_config
could be changed from PciConfigArch to PciRoot also, this could simplify code
and reduce two functions from PciConfigArch.
BUG=b:197877871
TEST=tools/presubmit
Change-Id: Ibc18587900d6f8259ac1d6f8fe7b3ea4fedad07e
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3305942
Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: Junichi Uekawa <uekawa@chromium.org>
Now that we have wired up PCI reset and exposed it via ACPI reset
register we no longer need to force resetting via keyboard port.
BUG=b:3169569
TEST=Reboot mantee board
Change-Id: I4bc02909199b3f519993794e28ed742432ebd64b
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3317156
Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: Dmitry Torokhov <dtor@chromium.org>
Instead of returning 0 for both shutdown and reset/reboot, let's have
shutdown continue returning 0, but reset will now return 32 exit code,
so that callers will have an option to handle this case differently.
BUG=b:3169569
TEST=Examine crosvm exit codes when resetting and shutting down VM
Change-Id: I2c7c11b7f8c8528744f7e25e5d17c6fa9810f409
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3316835
Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: Dmitry Torokhov <dtor@chromium.org>
This will allow guest OS to issue reset requests via ACPI methods.
BUG=b:3169569
TEST=Build and boot.
Change-Id: I6d29422f962c21a2e513cb4da78515e31468a1e5
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3316834
Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: Dmitry Torokhov <dtor@chromium.org>
This is a bit of a hack, but crosvm does not support overlapping IO/MMIO
regions, so we have to handle reset register in PciConfigIo handler
(which covers 0xcf8 - 0xcff range) instead of installing a dedicated
reset handler separate from PCI root handler.
BUG=b:3169569
TEST=Try rebooting Manatee booted with "reboot=p"
Change-Id: I79991f456d4aaaab2c904e312996208aa72ab6ec
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3316833
Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: Dmitry Torokhov <dtor@chromium.org>
Reserved 64MB mmio space for pcie enhanced configuration access,
and added it into mmio_bus with PciConfigMmio.
Now pci_root will be added into PciConfigIo and PciConfigMmio, so
Arc<Mux<pci_root>> is used.
BUG=b:197877871
TEST=tools/presubmit
Change-Id: Ic90a4cc3dfb00b09358478e129cc8a16e91012c6
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3305941
Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Junichi Uekawa <uekawa@chromium.org>
Commit-Queue: Junichi Uekawa <uekawa@chromium.org>
Hex memory regions usually are better expressed with 4 digits as one
compound.
BUG=b:188011323
TEST=None
Change-Id: Ic42fcbb6fd8c4ada5f0fb18c2ff41e3dbffb3408
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3312863
Commit-Queue: Junichi Uekawa <uekawa@chromium.org>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
Instead of open coding a loop, use any() method to check if we have
matching entries.
BUG=None
TEST=./tools/presubmit
Change-Id: Ib1fe7e65436bc3c8cca99be69855eb0ebc3cf096
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3313842
Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: Dmitry Torokhov <dtor@chromium.org>
The pci_irqs list contains an entry for each PCI device, but IRQ numbers
may be reused, so the MADT would contain duplicate interrupt override
entries in this case. This doesn't cause a problem in practice (the
duplicates are all identical and the guest kernel does not complain),
but it makes sense to remove the duplicates and only add a single
IOAPIC interrupt override entry per unique IRQ number.
BUG=b:207551552
TEST=x86_64 guest kernel only has 4 INT_SRC_OVR logs in dmesg
Change-Id: Iba4c57ca93d4be6c21e087b2f3f416fe022e8d35
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3315408
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: Daniel Verkamp <dverkamp@chromium.org>
Reviewed-by: Dmitry Torokhov <dtor@chromium.org>
Basic functionality works with a purely ACPI-based boot (no MPTable),
but something is still missing in the ACPI tables for describing the
full interrupt routing configuration. The guest kernel complains:
virtio-pci 0000:00:01.0: can't derive routing for PCI INT A
virtio-pci 0000:00:01.0: PCI INT A: no GSI
Restore the acpi=noirq option for now until we fill out the ACPI IRQ
descriptors correctly; this was a cleanup only and not required to fix a
bug.
This reverts commit cb464a7c08.
BUG=None
TEST=Boot Crostini; no interrupt routing failures in dmesg
Change-Id: Ib73c5749b48134124b3ebcb472706f087e8a85a2
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3315226
Reviewed-by: Dennis Kempin <denniskempin@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: Daniel Verkamp <dverkamp@chromium.org>
Now that we provide a correct MADT ("APIC" table ID), there is no need
to override the kernel ACPI option that made it ignore these tables.
BUG=None
TEST=Boot crosvm with setup_mptable() call removed, ACPI only
Change-Id: I9f4589738462c5693f151f60180c79d054a9084d
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3313841
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: Daniel Verkamp <dverkamp@chromium.org>
Reviewed-by: Dmitry Torokhov <dtor@chromium.org>
Reviewed-by: Dennis Kempin <denniskempin@google.com>
KVM's irqchip emulation provides the traditional PC-style pair of 8259
PICs, so report this by setting the appropriate flag in the MADT (APIC)
table.
BUG=b:207551552
TEST=Boot crosvm with setup_mptable() call removed
Change-Id: Ib5adf7ac717156deb3cd19d74873c9745ae826ec
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3313840
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: Daniel Verkamp <dverkamp@chromium.org>
Reviewed-by: Dmitry Torokhov <dtor@chromium.org>
Add interrupt redirection entries to MADT so that the legacy pin-based
interrupts are correctly reported as level triggered. This matches the
entries in the existing MPTable, but those are not availble when booting
with OVMF, which only provides ACPI tables.
This fixes an issue where USB device sharing was failing in some cases
when booted with ACPI only, since our xhci controller emulation only
supports pin-based interrupts (not MSI-X) and would not work correctly
when the guest incorrectly treated its IRQ as edge triggered.
BUG=b:207551552
TEST=Start crosvm with setup_mptable() call removed
TEST=Share USB device when booted with ACPI via OVMF
Change-Id: Id3e4ff5ba9587aadbeadbcc8eceaa771c4c2d5df
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3312577
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: Daniel Verkamp <dverkamp@chromium.org>
Reviewed-by: Dmitry Torokhov <dtor@chromium.org>
This function doesn't need to consume the pci_irqs vector, just iterate
over it.
BUG=None
TEST=tools/presubmit
Change-Id: Ibb66fa6ab8c45f58eeb89b976bcfc57e00d718a1
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3313996
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: Daniel Verkamp <dverkamp@chromium.org>
Reviewed-by: Dmitry Torokhov <dtor@chromium.org>
Reviewed-by: Dennis Kempin <denniskempin@google.com>
PcieRootPort implement hotplug_bus trait, it should be added into
RunnableLinuxVm->hotplug_bus, so create pcie root port when
RunnableLinuxVm->hotplug_bus is ready.
Many hotplug bus may exist, when a hotplug device is added, is_match()
should be called on each hotplug bus before attach that device to
the bus.
BUG=b:185084350
TEST=Boot a vm with passthrough device and check its function
Change-Id: I89dbc091f336b3f9d0435b52963f7cf62d408a67
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/2955570
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: Daniel Verkamp <dverkamp@chromium.org>
Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
There were not too many cases here. This fixes:
- comparison_chain
- wrong_self_convention
- upper_case_acronyms
- from_over_into
- let-and-return
The collapsible_if check is moved to the permanently
allowed checks. The cases we do have improve
readability or semantics.
BUG=chromium:908640
TEST=Kokoro
Change-Id: I6e905d08e2a87aa0862d4d1cf5ff57b60e95fa7d
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3278776
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: Dennis Kempin <denniskempin@google.com>
Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
Use the anyhow crate to provide ad-hoc errors with context. This removes
the large, manually-updated enum, which we never use programmatically
anyway (error messages are printed in human-readable form and otherwise
not matched against).
BUG=b:190433480
TEST=cargo build
TEST=./test_all
Change-Id: Ia7b90b33774d4031054b346d650861d3105044ee
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3105436
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: Daniel Verkamp <dverkamp@chromium.org>
Reviewed-by: Chirantan Ekbote <chirantan@chromium.org>
Original reason for revert: Causes crosvm to not start on AMD based devices b/204222491
Fixed by clamping the maximum physical address to 64 TiB, which is the
largest physical address supported by x86-64 Linux with only 4-level
page tables enabled.
In addition, the high MMIO region size calculation has been split into a
separate function, get_high_mmio_size(), and an off-by-one error in the
size calculation was fixed.
Original change's description:
> Devices: Allocate non pci bar mmio at top of HighMmio
>
> Some devices like virtio-pmem, intel host bridge need private mmio, these private
> mmio isn't exposed to Vm through pci bar, and crosvm use mmio allocation interface
> to allocate them, so guest OS pci bus driver couldn't detect them, and once guest
> OS reallocate pci mmio, these private mmmio could be assigned to pci device bar.
> then resource conflict happens.
>
> This patch allocates these non pci bar mmio at the top of HighMmio, since HighMmio
> is large enough and OS allocates pci mmio from low to high. So these non pci bar
> mmio won't conflict with pci bar.
>
> BUG=b:199442120
> BUG=b:185084350
> TEST=crosvm run --pmem-device xxxx
>
> Change-Id: I615d7901d595dd46ba6362f88b71d96baa9c4c8f
> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3184549
> Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
> Tested-by: kokoro <noreply+kokoro@google.com>
> Commit-Queue: Daniel Verkamp <dverkamp@chromium.org>
This is a reland of https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3184549
BUG=b:199442120
BUG=b:185084350
TEST=Crostini starts on grunt (AMD device)
TEST=crosvm run --pmem-device rootfs -p 'root=/dev/pmem0' kernel
Change-Id: I7c93f7132dbfbc3f38ecbfa0504b59214a1eb6bf
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3251788
Reviewed-by: Xiong Zhang <xiong.y.zhang@intel.corp-partner.google.com>
Reviewed-by: Dennis Kempin <denniskempin@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: Daniel Verkamp <dverkamp@chromium.org>
This change contains the results of running
./tools/contib/cargo_refactor.py
This will break the next uprev, and needs to be synchronizized
with the corresponding ebuild changes in https://crrev.com/c/3248925
BUG=b:195126527
TEST=./tools/run_tests
Change-Id: Ied15a1841887bb8f59fba65b912b81acf69beb73
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3248129
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: Dennis Kempin <denniskempin@google.com>
Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
This reverts commit 9557588786.
Reason for revert: Causes crosvm to not start on AMD based devices b/204222491
Original change's description:
> Devices: Allocate non pci bar mmio at top of HighMmio
>
> Some devices like virtio-pmem, intel host bridge need private mmio, these private
> mmio isn't exposed to Vm through pci bar, and crosvm use mmio allocation interface
> to allocate them, so guest OS pci bus driver couldn't detect them, and once guest
> OS reallocate pci mmio, these private mmmio could be assigned to pci device bar.
> then resource conflict happens.
>
> This patch allocates these non pci bar mmio at the top of HighMmio, since HighMmio
> is large enough and OS allocates pci mmio from low to high. So these non pci bar
> mmio won't conflict with pci bar.
>
> BUG=b:199442120
> BUG=b:185084350
> TEST=crosvm run --pmem-device xxxx
>
> Change-Id: I615d7901d595dd46ba6362f88b71d96baa9c4c8f
> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3184549
> Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
> Tested-by: kokoro <noreply+kokoro@google.com>
> Commit-Queue: Daniel Verkamp <dverkamp@chromium.org>
Bug: b:199442120
Bug: b:185084350
Change-Id: Ida1369bf0b70782633b1073ceef50e1bab108f55
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3248906
Bot-Commit: Rubber Stamper <rubber-stamper@appspot.gserviceaccount.com>
Commit-Queue: Dennis Kempin <denniskempin@google.com>
Rust bindgen now supports --allowlist and --blocklist option names as of
https://github.com/rust-lang/rust-bindgen/pull/1990 - use them in the
various bindgen invocations in scripts and comments.
BUG=b:178821708
TEST=../dev/contrib/search_blocked_words.sh unblocked_terms.txt
Change-Id: I9797f049999a01ab2c41617823463236b4d03cbb
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3243012
Reviewed-by: Dennis Kempin <denniskempin@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: Daniel Verkamp <dverkamp@chromium.org>
Some devices like virtio-pmem, intel host bridge need private mmio, these private
mmio isn't exposed to Vm through pci bar, and crosvm use mmio allocation interface
to allocate them, so guest OS pci bus driver couldn't detect them, and once guest
OS reallocate pci mmio, these private mmmio could be assigned to pci device bar.
then resource conflict happens.
This patch allocates these non pci bar mmio at the top of HighMmio, since HighMmio
is large enough and OS allocates pci mmio from low to high. So these non pci bar
mmio won't conflict with pci bar.
BUG=b:199442120
BUG=b:185084350
TEST=crosvm run --pmem-device xxxx
Change-Id: I615d7901d595dd46ba6362f88b71d96baa9c4c8f
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/3184549
Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: Daniel Verkamp <dverkamp@chromium.org>
